Abstract: A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Abstract: A method of controlling gear shifting in an electric vehicle includes: determining whether or not an electric vehicle travels in an electric vehicle (EV) traveling mode; determining whether or not kick-down gear shifting is required in the EV traveling mode; determining whether or not acceleration linearity control is possible, in a case where the kick-down gear shifting is required; performing correction of a torque of a motor in a case where the acceleration linearity control is possible; and performing gear shifting in a transmission on the basis of the corrected torque of the motor.

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Abstract: A method of detecting a urine test strip from a photographed image of the urine test strip is disclosed. The disclosed method of detecting a urine test strip includes: receiving input of a urine test strip image, which is a photographed image of a urine test strip including a first and a second marker; detecting a first and a second marker image within the urine test strip image; detecting an area between the first and second marker images within the urine test strip image; and detecting a reagent pad and a colorimetric table in the urine test strip image by matching an area of interest, which represents a position of the reagent pad and the colorimetric table in the urine test strip image, with the area between the first and second marker images.

Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.

Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: A mobility hub is composed of a plurality of layers and serves as a terminal of a ground mobility and an air mobility. The mobility hub includes: a ground layer provided with an entrance of the ground mobility; a port layer provided with a taking-off and landing site of the air mobility; and a middle layer provided between the ground layer and the port layer. The middle layer has the ground mobility elevating in a space with the ground layer, is provided with a plurality of connection slots to which the ground mobility is connected, and provides an activity space through the ground mobility if the ground mobility is coupled to the connection slot.

Abstract: A semiconductor device includes a first active region, a second active region, a first gate line disposed to overlap the first and second active regions, a second gate line disposed to overlap the first and second active regions, a first metal line electrically connecting the first and second gate lines and providing a first signal to both the first and second gate lines, a first contact structure electrically connected to part of the first active region between the first and second gate lines, a second contact structure electrically connected to part of the second active region between the first and second gate lines, and a second metal line electrically connected to the first and second contact structures and transmitting a second signal, wherein an overlapped region that is overlapped by the second metal line does not include a break region.

Abstract: A touch display device for preventing the occurrence of a short circuit between routing lines is disclosed. The touch display device includes a dam forming a boundary with an encapsulation unit covering a light-emitting element, and the dam is formed such that the height thereof in a region that overlaps routing lines, which are connected to touch electrodes disposed on the encapsulation unit, and the height thereof in a region that does not overlap the routing lines are different from each other, thereby preventing the occurrence of a short circuit between the routing lines.

Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

Abstract: A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

Abstract: A coating device according to one embodiment of the present invention is a device for coating, with a paint, a target surface which is at least a part of a wall surface of a building, and comprises: a first movement part that can move in the vertical direction in accordance with a change in the length of a wire by driving of a winch drum; and a spraying part that can move in the left or right direction along the first movement part, and directly sprays the paint on the target surface or sprays the paint on a coating roller that rotates in contact with the target surface, such that a range from a predetermined left line to a predetermined right line of the target surface with reference to the left and right directions can be coated with the paint.

Abstract: A pulse sensing module used in a blood pressure measuring device attached to the skin to allow at least one of systolic pressure Psystolic, diastolic pressure Pdiastolic, and blood pressure variation to be measured according to an embodiment of the present disclosure includes a piezoelectric layer that includes a piezoelectric material for generating a piezoelectric effect due to a pulse and a protective layer that is applied to the piezoelectric layer to protect the piezoelectric layer, allows a poling process of applying a high voltage to the first electrode line and the second electrode line formed on the piezoelectric layer to improve the polarity of the piezoelectric material, and has an opening for allowing a portion of the first electrode line and a portion of the second electrode line to be exposed.

Abstract: A smart home service which is capable of providing an environment in which calling a control command for a device is available via a user terminal protocol to control between the device and a user terminal based on different type of protocol and a control method for the same. The smart home service server connecting at least one device operated based on a first protocol to at least one user terminal operated based on a second protocol, includes an application programming interface (API) controller configured to allow a control command for the at least one device to be called via the second protocol of the at least one user terminal; a filter configured to convert the called control command according to the first protocol; and a control command transmitter configured to transmit the control command converted according to the first protocol, to the at least one device.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

Abstract: An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.