Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. Metal fill, such as copper, is formed within a portion of the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices and towards a heat spreader.

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device, and integrated inductors formed over the semiconductor devices. Power delivery to the device is on the opposite side of the semiconductor devices. The integrated inductors may be used for power step-down to reduce device thickness and/or a number of power rails.

Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.

Abstract: A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

Abstract: A memory subsystem triggers dynamic switching for memory devices to provide access to active memory devices and prevent access to inactive memory devices. Dynamic switching enables a single bus to switch between multiple memory devices whose capacity otherwise exceeds the capacity of the single bus. A switch can be mounted in a memory module or directly on a motherboard alongside the memory devices. A memory controller can toggle a chip select signal as a single control signal to drive the switch. Each switch includes pairs of field effect transistors (FETs), including any of CMOS, NMOS and PMOS FETs. The switch electrically isolates inactive memory devices to prevent access without the need to electrically short the devices.

Abstract: A semiconductor package including a package substrate including a bottom surface; a first plurality of solder balls connected to the bottom surface of the package substrate; a second plurality of solder balls connected to a motherboard; and a shielding assembly interposed between the first and the second plurality of solder balls and configured to shield each solder ball of the first and second plurality of solder balls from electromagnetic interference.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes for stiffeners for a surface of a package substrate, where the stiffeners provide EMI/RFI shielding for signal traces or other electrical routings within the package, and in particular for traces at a surface of the package such as microstrip routings. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die. In an embodiment, a package substrate is coupled to the die. In an embodiment, a ring is provided under the package substrate. In an embodiment, the ring comprises a conductive material. In an embodiment, the electronic package further comprises balls outside of the ring.

Abstract: Embodiments herein relate to systems, apparatuses, or processes for creating packages that include one or more memory modules with electrically conductive strips on the side of the memory module to route power or provide a ground to multiple BGA contacts on a side of the memory module coupled with a substrate. Providing power and/or ground in this manner enables fewer layers to be used in a substrate that are no longer needed to be routed in the power plane on the substrate, thus reducing a Z-height of the package. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a die complex with a base die that is coupled with a HDP substrate that in turn is coupled with an mSAP board. The HDP substrate may have a small trace width and trace spacing, for example three ?m or less, that enable the HDP substrate to be used as a pitch translator between the base die and the mSAP board, for example between a 110 ?m pitch and a 210 ?m pitch. One or more DRAM modules may be coupled with the mSAP board. The configuration has a reduced overall package height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to an electrical conductor, or power corridor, on the outside of a package substrate, wherein the electrical conductor is raised, or extends from a surface of the package substrate. In embodiments, this electrical conductor may be used to reduce the number of layers required within the package substrate by removing power planes within the substrate to the electrical conductors on the surface of the package. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package. In embodiments, the gasket may include a material that blocks or absorbs EMI or RFI. Other embodiments may be described and/or claimed.

Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.

Abstract: A substrate to printed circuit board (PCB) interconnect with liquid metal and surface pins. A thin dielectric sheet with drilled openings is adjacent to the bottom of a system on chip or CPU package substrate. Holes in the dielectric sheet have a liquid metal (LM) therein, the holes correspond to landing metal pads on the package substrate. The PCB includes surface pins in an arrangement to match the LM filled holes. A pick and place assembly of the package substrate to the PCB can be done without needing a reflow step. A magnet ring can be positioned on the polyimide sheet and configured to pair with a metal plate on the PCB. Guideposts around the periphery of the package substrate may be used to assist in alignment during assembly.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a base coupled to the package substrate. In an embodiment, a die is coupled to the base, and a memory die module is over the die.

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a cutout. In an embodiment, pads are adjacent to the cutout. In an embodiment, a memory die stack is on the package substrate, where the memory die stack is electrically coupled to the pads by routing in the package substrate. In an embodiment, a die is over the cutout, where the die is supported by the pads.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a first memory die stack on the package substrate, and a second memory die stack on the package substrate. In an embodiment, an electrically insulating layer is provided over the first memory die stack and the second memory die stack. In an embodiment, an opening is provided through the electrically insulating layer, and a die module is in the opening over the package substrate.

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.