Abstract: A test mode control circuit includes an encryption circuit and a test mode generating circuit. The encryption circuit encrypts, based on an encryption code, an access code set to generate an encrypted access code set. The test mode generating circuit generates a test mode signal based on the encrypted access code set.

Abstract: The present invention relates to a novel use of NCKAP1 gene in neurodegenerative diseases. More specifically, the present invention relates to a marker composition for predicting the prognosis of a neurodegenerative disease, comprising a NCKAP1 protein or a gene encoding same, a composition and a kit for predicting the prognosis of a neurodegenerative disease, which comprises a formulation for measuring the level of the protein or an mRNA of the gene encoding same, and a pharmaceutical composition for preventing or treating neurodegenerative disease, comprising the protein or the gene encoding same as an active ingredient.

Abstract: A lighting device includes a light guide plate configured to guide and diffuse a light from a light source, and a garnish body including a lighting area to which the diffused light is radiated, wherein the light guide plate is disposed at a predetermined angle with respect to the garnish body.

Abstract: The present invention relates to a method for preparing a sulfide-based solid electrolyte, a sulfide-based solid electrolyte prepared by the method, and an all-solid-state lithium secondary battery including the sulfide-based solid electrolyte. The method of the present invention includes a) mixing Li2S with P2S5 to prepare a mixed powder, b) placing the mixed powder, an ether, and stirring balls in a container, sealing the container, followed by stirring to prepare a suspension, and c) stirring the suspension under high-temperature and high-pressure conditions to prepare sulfide-based solid particles.

Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.

Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.

Abstract: An address control circuit includes an address timing control circuit configured to latch address signals inputted from outside the address timing control circuit, sequentially store the latched signals at predetermined timings, and output the stored signals as a bank group address. The address control circuit also includes an address multiplexing circuit configured to generate bank group select signals according to the bank group address. The address multiplexing circuit is configured to generate the bank group select signals having a second value according to the bank group address having a first value when a preset memory access mode is a first memory access mode, and generate the bank group select signals having the second value according to the bank group address having a third value different from the first value when the preset memory access mode is a second memory access mode.

Abstract: A semiconductor device includes a read/write control circuit, a core circuit, and a data conversion circuit. The read/write control circuit generates a read strobe signal and a read address from an internal address/command signal based on an internal read command during a self-write operation, generates a write strobe signal after the read strobe signal is generated, and generates a write address from the internal address/command signal. The core circuit is synchronized with the read strobe signal to output read data stored in a bank selected by the read address and is synchronized with the write strobe signal to store write data into the bank or another bank which is selected by the write address. The data conversion circuit changes a pattern of the read data to generate the write data.

Abstract: A semiconductor device includes a read/write control circuit, a core circuit, and a data conversion circuit. The read/write control circuit generates a read strobe signal and a read address from an internal address/command signal based on an internal read command during a self-write operation, generates a write strobe signal after the read strobe signal is generated, and generates a write address from the internal address/command signal. The core circuit is synchronized with the read strobe signal to output read data stored in a bank selected by the read address and is synchronized with the write strobe signal to store write data into the bank or another bank which is selected by the write address. The data conversion circuit changes a pattern of the read data to generate the write data.

Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.

Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: A semiconductor device includes a flag pipe, a pattern mode control circuit, and a data copy control circuit. The flag pipe is configured to latch a pattern mode flag, a first pattern control flag, a second pattern control flag, a data copy flag, and an enlargement data copy flag based on a pipe input control signal and output a delayed pattern mode flag, a first delayed pattern control flag, a second delayed pattern control flag, and a synthesis data copy flag based on a pipe output control signal. The pattern mode control circuit is configured to set a first data pattern or a second data pattern based on the delayed pattern mode flag, the first delayed pattern control flag, and the second delayed pattern control flag. The data copy control circuit is configured to copy data inputted through a first data pad onto a data path electrically connected to a second data pad based on the synthesis data copy flag.

Abstract: A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

Abstract: This invention relates to a Te-based thermoelectric material having stacking faults by addition of an interstitial dopant, including unit cells configured such that A-B-A-C-A elements are stacked to five layers, in which A element of a terminal of a unit cell and A element of a terminal of another unit cell are repeatedly stacked by a van der Waals interaction, wherein an interstitial element as the dopant is located at an interstitial position between the repeatedly stacked A elements adjacent to each other, thus generating stacking faults of the repeatedly stacked unit cells to thereby form a twin as well as a complex crystal structure different from the unit cells (where A is Te or Se, B is Bi or Sb, and C is Bi or Sb).

Abstract: Disclosed herein are a method for manufacturing a functional material for use in various industrial fields in which anisotropy or physical properties change according to height may be utilized, as well as a functional material manufactured thereby. The method includes the steps of: (1) mixing powders composed of the components of the functional material with a binder to prepare a mixed paste; (2) coating the mixed paste on a substrate, and then separating the coated material from the substrate, thus preparing a slice; (3) repeating step (2) to prepare a plurality of slices, and stacking the slices in a mold; and (4) pressing the stacked slices at a predetermined temperature and pressure. A multifunctional material, such as an anisotropic material having physical properties which change according to the direction of material, or a material having physical properties which change in a graduated manner according to height, may be manufactured in a simple and economical manner.

Abstract: Disclosed herein is a thermoelectric material for intermediate- and low-temperature applications, in which any one or a mixture of two or more selected from among La, Sc and MM is added to a Ag-containing metallic thermoelectric material or semiconductor thermoelectric material. The thermoelectric material has a low thermal diffusivity, a high Seebeck coefficient, a low specific resistivity, a high power factor and a low thermal conductivity, and thus has a high dimensionless figure of merit, thus showing very excellent thermoelectric properties. The thermoelectric material provide thermoelectric sensors having high sensitivity and low noise and, in addition, is widely used as a thermoelectric material for intermediate- and low-temperature applications, because it shows excellent thermoelectric performance in the intermediate- and low-temperature range.

Abstract: Disclosed herein are a method for manufacturing a functional material for use in various industrial fields in which anisotropy or physical properties change according to height may be utilized, as well as a functional material manufactured thereby. The method includes the steps of: (1) mixing powders composed of the components of the functional material with a binder to prepare a mixed paste; (2) coating the mixed paste on a substrate, and then separating the coated material from the substrate, thus preparing a slice; (3) repeating step (2) to prepare a plurality of slices, and stacking the slices in a mold; and (4) pressing the stacked slices at a predetermined temperature and pressure. A multifunctional material, such as an anisotropic material having physical properties which change according to the direction of material, or a material having physical properties which change in a graduated manner according to height, may be manufactured in a simple and economical manner.