Abstract: A one-time programmable (OTP) memory device including: a cell array circuit including an OTP cell array and dummy cell block, the OTP cell array includes OTP memory cells coupled to bit-lines, read word-lines and voltage word-lines and the dummy cell block is coupled to the read word-lines and voltage word-lines; a row decoder coupled to the dummy cell block and the OTP cell array through the read word-lines and voltage word-lines; a column decoder coupled to the OTP cell array through the bit-lines; a write-sensing circuit coupled to the column decoder; and a control circuit to control the cell array circuit, row decoder and write-sensing circuit based on a command and address, the cell array circuit further includes an isolation circuit to cut off first and second voltages which are transferred to the OTP cell array from the row decoder, in response to control codes in a test mode.

Abstract: A one-time programmable (OTP) memory cell, and an OTP memory and a memory system including the same may be provided. The OTP memory cell includes a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a second node. The OTP memory cell is configured to apply a program voltage to gates of the main OTP cell transistor and the redundant OTP cell transistor, and a program access voltage lower than the program voltage to a gate of the access transistor, during a program operation.

Abstract: A one-time programmable (OTP) memory cell, and an OTP memory and a memory system including the same may be provided. The OTP memory cell includes a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a second node. The OTP memory cell is configured to apply a program voltage to gates of the main OTP cell transistor and the redundant OTP cell transistor, and a program access voltage lower than the program voltage to a gate of the access transistor, during a program operation.

Abstract: A one-time programmable (OTP) memory device including: a cell array circuit including an OTP cell array and dummy cell block, the OTP cell array includes OTP memory cells coupled to bit-lines, read word-lines and voltage word-lines and the dummy cell block is coupled to the read word-lines and voltage word-lines; a row decoder coupled to the dummy cell block and the OTP cell array through the read word-lines and voltage word-lines; a column decoder coupled to the OTP cell array through the bit-lines; a write-sensing circuit coupled to the column decoder; and a control circuit to control the cell array circuit, row decoder and write-sensing circuit based on a command and address, the cell array circuit further includes an isolation circuit to cut off first and second voltages which are transferred to the OTP cell array from the row decoder, in response to control codes in a test mode.

Abstract: A refresh control circuit includes a reference voltage generating circuit and an oscillator unit. The reference voltage generating circuit generates a reference voltage based on a variation in a drain-to-source voltage of a field effect transistor according to a temperature variation. The oscillator unit generates a pulse signal having a period that varies according to the temperature based on the reference voltage. The refresh period is thereby controlled automatically, in accordance with the operating temperature.

Abstract: An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.

Abstract: The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.

Abstract: A refresh control circuit includes a reference voltage generating circuit and an oscillator unit. The reference voltage generating circuit generates a reference voltage based on a variation in a drain-to-source voltage of a field effect transistor according to a temperature variation. The oscillator unit generates a pulse signal having a period that varies according to the temperature based on the reference voltage. The refresh period is thereby controlled automatically, in accordance with the operating temperature.

Abstract: An integrated circuit memory device includes a plurality of memories and a refresh controller within a memory system. The refresh controller is configured to generate a refresh request signal. The plurality of memories includes a plurality of banks of memory responsive to the refresh request signal. An additional memory includes a buffer unit configured to generate a refresh indication signal to a first one of the plurality of banks of memory and to receive buffer write data addressed to the first one of the plurality of banks of memory in response to receiving a refresh-access interrupt signal from the one of the plurality of banks of memory. The plurality of banks of memory and the buffer unit may be separate DRAM chips.

Abstract: The present invention provides a memory and memory control system wherein, except for one case noted below, the main memory gives priority to read or write operations over refresh operations. On the other hand, the cache memory give priority to the refresh operations over read or write operations. The exceptional case is when a memory read signal is received when the cache refresh is enabled and the data in the cache memory is valid. In this exceptional case, the refresh of the cache memory is delayed. During certain read operations the data in the particular memory block is also written to the cache and no write back from the cache is performed. This reduces the number of write back operations and it eliminates a delay due to the refresh operation.