Patents by Inventor Min-Yuan Tsai

Min-Yuan Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION
    Publication number: 20150379189
    Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
    Type: Application
    Filed: August 6, 2015
    Publication date: December 31, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung Lung LIN, Chin-Chang HSU, Min-Yuan TSAI, Wen-Ju YANG, Chien Lin HO
  • Triple-pattern lithography layout decomposition
    Patent number: 9122838
    Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai, Wen-Ju Yang, Chien Lin Ho
  • TRIPLE-PATTERN LITHOGRAPHY LAYOUT DECOMPOSITION
    Publication number: 20140372958
    Abstract: Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Hung Lung LIN, Chin-Chang HSU, Min-Yuan TSAI, Wen-Ju YANG, Chien Lin HO
  • Triple-pattern lithography layout decomposition validation
    Patent number: 8875065
    Abstract: A method of decomposing a layout for triple pattern lithography generates a first conflict graph from the layout. The method generates a second conflict graph from the first conflict graph, and identifies loops in the second conflict graph as decomposition violations.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Lung Lin, Chin-Chang Hsu, Min-Yuan Tsai, Wen-Ju Yang
  • Stretch dummy cell insertion in FinFET process
    Patent number: 8869090
    Abstract: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Sheng Ke, Min-Yuan Tsai, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang
  • Stretch Dummy Cell Insertion in FinFET Process
    Publication number: 20140258961
    Abstract: A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 11, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Sheng Ke, Min-Yuan Tsai, Jia-Rong Hsu, Hung-Lung Lin, Wen-Ju Yang