Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

Abstract: Provided is a “castled” active area mask. A castled active area mask is one which has been lengthened to extend beyond its intended intersection with a tunnel dielectric to form the tunnel window of an EEPROM cell, and has also been widened in at least a portion of the extension. For example, in one preferred embodiment, a castled extension may have a “T” shape. The castled active area generated by such a mask provides a buffer to absorb field oxide encroachment before it reaches the EEPROM cell's TD window. A mask in accordance with the present invention may be used to fabricate EEPROM cells which are not subject to TD window size variations due to field oxide encroachment, and EEPROM cell arrays of increased density.

Abstract: Disclosed is a method for biasing dual row line EEPROM cells. The new biasing scheme improves the data retention lifetime of an EEPROM cell by reducing the potential difference between the control gate and the write column of the cell, which reduces the tunnel oxide electric field. In a preferred embodiment, the method involves applying bias voltages to the control gate and write column of an EEPROM cell such that the potential difference between the control gate and the right column is no more than about 0.5 volts. By biasing the cell's write column to a positive voltage, the tunnel oxide field may be significantly reduced. Moreover, the invention provides a method of selecting a write column voltage based on a control gate voltage such that the tunnel oxide field is substantially balanced in all its modes. This biasing scheme minimizes SILC and improves cell reliability.