Abstract: A method for concurrent search and select of routing patterns for a routing system is provided. The provided method introduces a metric for indicating the goodness of a routing pattern for guiding the selection of search engine at the route finding stage. Next, the method explores routes based on a plurality of feasible routing track segments that represent the longest continuous span of possible routes on a routing layer. Next, the preferred routing patterns can be selected. After that, the method goes to find one or more routing violations and then avoid the routing violations. Furthermore, the avoidance of the routing violation(s) can be implemented by reducing the length of the feasible routing track segment, or removing portion of a routed segment running in parallel and adjacent track(s) of the feasible routing track segment.

Abstract: The invention details apparatus for rapid calculation of models for routing patterns. The calculation comprises learning or self-adapting mechanisms to gradually improve its accuracy. The outputs from such calculation can be used by a routing system to select routing patterns to control variations from manufacturing process. Depending on the model selection, the application areas include but not limited to yield, process window, and timing variations.

Abstract: The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power; manufacturing process variations; and measured silicon data. In one embodiment, the model can be described as input to the system and the model calculator can interact either with the data structure or the query engine of the detail router or both. The model calculator can accept input as a set of geometry description and produce output to guide the query functions. An example technique called set intersection is disclosed herein to combine multiple models in the system. A preferred embodiment of this invention includes a full chip grid-based router being aware of manufacturability.

Abstract: A method and apparatus for integrated circuit layout optimization are provided. In the conventional art, the major challenges in building integrated circuits (IC) at sub-wavelength geometries include i) to ensure the design intent is faithfully transferred onto silicon; ii) to ensure the design is manufacturable, or with acceptable yield subject to process variations. The present invention provides the method to process a layout database to optimize or correct or fix layout violations or enhancements. The layout violations are identified through various means such as design rules, recommended rules, timing/signal integrity/power constraints, lithography rules, Resolution Enhancement Technologies (RET) requirements and preferences, and process and manufacturing constraints. Particularly, the method, techniques and procedures of creating software tools of the present invention used to perform the layout violations or enhancements are disclosed.