Patents by Inventor Minesh S. Desai

Minesh S. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Controlling the timing of test modes in a multiple processor system
    Patent number: 7100033
    Abstract: A system includes a first processor, a second processor and a circuit. The first processor includes a first terminal and enters a first test mode in response to the first terminal having a first signal state. The second processor includes a second terminal. The second processor enters a second test mode in response to the second terminal having a second signal state. The circuit may regulate the timing of the first and second signal states to place both the first processor in the first test mode and the second processor in the second test mode at approximately the same time. The circuit may regulate the timing of the signals to cause the first and second processors to resume normal modes of operation at approximately the same time.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Charles P. Roth, Minesh S. Desai, Gerold Mueller, Peter Lachner
  • Controlling the timing of test modes in a multiple processor system
    Publication number: 20040083072
    Abstract: A system includes a first processor, a second processor and a circuit. The first processor includes a first terminal and enters a first test mode in response to the first terminal having a first signal state. The second processor includes a second terminal. The second processor enters a second test mode in response to the second terminal having a second signal state. The circuit may regulate the timing of the first and second signal states to place both the first processor in the first test mode and the second processor in the second test mode at approximately the same time. The circuit may regulate the timing of the signals to cause the first and second processors to resume normal modes of operation at approximately the same time.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Inventors: Charles P. Roth, Minesh S. Desai, Gerold Mueller, Peter Lachner