Patents by Inventor Ming Chang Lu

Ming Chang Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120363
    Abstract: A self-aligned plug may be formed between deep trench isolation (DTI) etching cycles. Accordingly, etch depth in areas of a pixel sensor with large CDs (e.g., at an X-road) is reduced, which prevents trench loading. As a result, a floating diffusion (FD) region, associated with photodiodes of the pixel sensor, is not damaged during the DTI etching cycles. Reduced chances of damage to the FD region improves performance of the pixel sensor and prevents electrical shorts and failures, which increases yield and conserves time and raw materials used in forming the pixel sensor.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 11, 2024
    Inventors: Ming-Chyi LIU, Jiech-Fun LU, Shih-Chang LIU, Ru-Liang LEE
  • Publication number: 20230083904
    Abstract: A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.
    Type: Application
    Filed: October 14, 2021
    Publication date: March 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Ming-Chang Lu
  • Patent number: 11450747
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Publication number: 20210242018
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer, including a substrate, a blocking layer on said substrate, wherein said blocking layer is provided with predetermined recess patterns, multiple recesses formed in said substrate, wherein each of said multiple recesses is in 3D diamond shape with a centerline perpendicular to a surface of said substrate, a buffer layer on a surface of each of said multiple recesses, and an epitaxial layer comprising a buried portion formed on said buffer layer in each of said multiple recesses and only one above-surface portion formed directly above said blocking layer and directly above said recess patterns of said blocking layer, and said above-surface portion directly connects said buried portion in each of said multiple recesses, and a first void is formed inside each of said buried portions of said epitaxial layer in said recess.
    Type: Application
    Filed: March 30, 2021
    Publication date: August 5, 2021
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Patent number: 11011376
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and an above-surface portion formed on the blocking layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Patent number: 10861970
    Abstract: A semiconductor epitaxial structure with reduced defects, including a substrate with a recess formed thereon, an island insulator on a bottom surface of the recess, spacers on sidewalls of the recess, a buffer layer in the recess and covering the island insulator, a channel layer in the recess and on the buffer layer, and a barrier layer in the recess and on the channel layer, wherein two-dimensional electron gas (2DEG) or two-dimensional hole gas (2DHG) is formed in the channel layer.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 8, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ming Chang, Chun-Liang Hou, Wen-Jung Liao, Ming-Chang Lu
  • Publication number: 20200194252
    Abstract: The present invention discloses a semiconductor structure with an epitaxial layer and method of manufacturing the same. The semiconductor structure with the epitaxial layer includes a substrate, a blocking layer on the substrate, multiple recesses formed in the substrate, wherein the recess extends along <111> crystal faces of the substrate, and an epitaxial layer on the blocking layer, wherein the epitaxial layer is provided with a buried portion in each recess and a surface portion formed on the blocking layer.
    Type: Application
    Filed: January 8, 2019
    Publication date: June 18, 2020
    Inventors: Hsiao-Pang Chou, Hon-Huei Liu, Ming-Chang Lu, Chin-Fu Lin, Yu-Cheng Tung
  • Patent number: 10672681
    Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chang Lin, Hsin-Yu Pan, Lipu Kris Chuang, Ming-Chang Lu
  • Publication number: 20190333836
    Abstract: Semiconductor packages are provided. One of the semiconductor packages includes a first sub-package and a second sub-package. The first sub-package includes a first die, a graphite oxide layer on the first die and an encapsulant encapsulating the first die and the graphite oxide layer. The second sub-package is stacked on and electrically connected to the first sub-package, and includes a second die. The graphite oxide layer is disposed between the first die and the second die.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Chang Lin, Hsin-Yu Pan, Lipu Kris Chuang, Ming-Chang Lu
  • Patent number: 10290710
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Patent number: 10283614
    Abstract: Provided is a semiconductor structure including a substrate, a first semiconductor layer, a second semiconductor layer, a gate electrode, a source electrode and a drain electrode. The first semiconductor layer contains a group III-V-VI semiconductor compound layer and is disposed on the substrate. The second semiconductor layer includes a group III-V semiconductor compound and is disposed on the first semiconductor layer. The gate electrode is disposed on the second semiconductor layer. The source electrode and the drain electrode are disposed on the second semiconductor layer beside the gate electrode.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 7, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Chang Lu, Wei Chen
  • Patent number: 10258597
    Abstract: A method for treating a glycoprotein-related disease is disclosed, which comprises: administering a first effective amount of phenol red and a second effective amount of an organic arsenic compound to a subject in need thereof.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 16, 2019
    Inventor: Ming-Chang Lu
  • Publication number: 20190074357
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Publication number: 20190030852
    Abstract: The present disclosure illustrates a microgroove structure for controlling frost nucleation, and the microgroove structure has a substrate which has a non-rough surface. The non-rough surface has one or more microgrooves extending along a first direction. The microgroove structure for controlling frost nucleation has nice anti-icing and deicing performances.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 31, 2019
    Inventors: Ming-Chang Lu, Ching-Wen Lo
  • Patent number: 10154985
    Abstract: A method for treating a glycoprotein-related disease is disclosed, which comprises: administering a first effective amount of phenol red and a second effective amount of an organic arsenic compound to a subject in need thereof.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: December 18, 2018
    Inventor: Ming-Chang Lu
  • Publication number: 20180346782
    Abstract: A working fluid in cooperation with a solar thermal system comprises a heat conduction medium and a plurality of metal particles mixed in the heat conduction medium. Each of the metal particles includes a metal particle and a protection layer, and the protection layer is an oxide and covers the metal particle. A manufacturing method of metal particles is also disclosed.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 6, 2018
    Inventors: Yu-Lun CHUEH, Ming-Chang LU
  • Patent number: 10077390
    Abstract: A working fluid in cooperation with a solar thermal system comprises a heat conduction medium and a plurality of metal particles mixed in the heat conduction medium. Each of the metal particles includes a metal particle and a protection layer, and the protection layer is an oxide and covers the metal particle. A manufacturing method of metal particles is also disclosed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: September 18, 2018
    Assignee: National Tsing Hua University
    Inventors: Yu-Lun Chueh, Ming-Chang Lu, Chih-Chung Lai, Shih-Ming Lin, Yuan-Da Chu
  • Publication number: 20180085336
    Abstract: A method for treating a glycoprotein-related disease is disclosed, which comprises: administering a first effective amount of phenol red and a second effective amount of an organic arsenic compound to a subject in need thereof.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventor: Ming-Chang Lu
  • Publication number: 20170049742
    Abstract: A method for treating a glycoprotein-related disease is disclosed, which comprises: administering a first effective amount of phenol red and a second effective amount of an organic arsenic compound to a subject in need thereof.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 23, 2017
    Inventor: Ming-Chang LU
  • Publication number: 20150322323
    Abstract: A working fluid in cooperation with a solar thermal system comprises a heat conduction medium and a plurality of metal particles mixed in the heat conduction medium. Each of the metal particles includes a metal particle and a protection layer, and the protection layer is an oxide and covers the metal particle. A manufacturing method of metal particles is also disclosed.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: Yu-Lun CHUEH, Ming-Chang LU, Chih-Chung LAI, Shih-Ming LIN, Yuan-Da CHU