Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal

Abstract: The disclosure provides a data privacy protection method, a server device, and a client device for federated learning. A public dataset is used to perform model training on a machine learning model by a server device to generate a gradient pool including multiple first gradients. The gradient pool and the machine learning model are received by a client device. The client device uses a local dataset to perform model training on the machine learning model to obtain a second gradient. A local gradient is selected from the first gradients in the gradient pool according to the second gradient using a differential privacy algorithm by the client device. An aggregated machine learning model is generated by performing model aggregation based on the local gradient by the server device.

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: An electronic device including a protective substrate is provided. The protective substrate includes a substrate and an anti-reflection layer. The anti-reflection layer is disposed on the substrate. The anti-reflection layer includes a first sublayer to an nth sublayer sequentially arranged on the substrate, where n is greater than 1, and a product range of a thickness and a refractive index of the nth sublayer ranges from 100 nm to 170 nm.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: The present disclosure provides a method for preparing a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors, the composition prepared by the method, and use of the composition for treating arthritis. The composition of the present disclosure achieves the effect of treating arthritis through various efficacy experiments.

Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.

Abstract: In order to reduce the occurrence of current alarms in a semiconductor etching or deposition process, a controller determines an offset in relative positions of a cover ring and a shield over a wafer within a vacuum chamber. The controller provides a position alarm and/or adjusts the position of the cover ring or shield when the offset is greater than a predetermined value or outside a range of acceptable values.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.

Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.

Abstract: A heat-dissipating net structure disposed in a vapor chamber unit includes latitudinal strand units and longitudinal strand units crossing each other. Each latitudinal strand unit has a single latitudinal strand extending in a first direction. Each longitudinal strand unit has at least two longitudinal strands extending in a second direction different from the first direction, with the longitudinal strands passing over and under the latitudinal strand units and twisting densely in the second direction to form a plurality of crossing points between the longitudinal strands because of the twisting arrangement. The twisting arrangement of the longitudinal strands prevents unnecessary spaces formed between any two adjacent longitudinal strand units, improves the capillary phenomenon of working fluid within the vapor chamber unit, and facilitates the phase transition of the working fluid, thereby attaining the effect of dissipating heat quickly.

Abstract: A BLDC motor driver circuit includes: a driving power stage circuit configured to provide a start-up test signal in a start-up mode to excite a BLDC motor, to drive a rotor of the BLDC motor to rotate for a test; a current unidirectional circuit coupled to the BLDC motor at a reverse end for detecting a BEMF, to generate a detection signal at a forward end of the current unidirectional circuit, wherein when a voltage at the reverse end exceeds a voltage at the forward end, the current unidirectional circuit limits the voltage at the forward end not to be higher than a clamp voltage; a biasing circuit for biasing the current unidirectional circuit in a forward operation state and for providing the clamp voltage; and a sensor circuit for generating a sensing signal according to the detection signal to indicate a test rotation state of the BLDC motor.

Abstract: A braiding apparatus includes a platform, a base plate, a core unit, a transmission unit, a track assembly, and strand carriers. The track assembly is divided into two braiding track groups each provided with transmission discs. The transmission discs of both braiding track groups are sequentially connected to define two braiding routes. The strand carriers shuttle on both braiding routes respectively and incessantly. Two intersection points are defined when the two braiding routes intersect. Accordingly, carrier strands fed by the strand carriers are wound around a core strand fed by the core unit while shuttling incessantly and are interwoven with each other while passing through the two intersection points during the incessant shuttling motion, thereby wrapping a multi-convolutional braided layer around the core strand to complete a rope. Each convolution of the braided layer has two crossing points, which increases the practicability of the rope.

Abstract: A braiding apparatus includes a platform, a base plate, a core unit, a transmission unit, a track assembly, and strand carriers. The track assembly is divided into two braiding track groups each provided with transmission discs. The transmission discs of both braiding track groups are sequentially connected to define two braiding routes directed in different directions. The strand carriers shuttle on both braiding routes respectively and incessantly. Four intersections are defined when the two braiding routes meets. Accordingly, carrier strands fed by the strand carriers are wound around a core strand fed by the core unit while shuttling incessantly and are interwoven with each other while passing through the four intersections during the incessant shuttling motion, thereby wrapping a multi-convolutional braided layer around the core strand to complete a rope. Each convolution of the braided layer has four crossing points, which increases the practicability of the rope.

Abstract: A braiding apparatus includes a platform, a base plate, a core unit, a transmission unit, a track assembly, and strand carriers. The track assembly is divided into two braiding track groups each provided with transmission discs. The transmission discs of both braiding track groups are sequentially connected to define two braiding routes. The strand carriers shuttle on both braiding routes respectively and incessantly. Two intersection points are defined when the two braiding routes intersect. Accordingly, carrier strands fed by the strand carriers are wound around a core strand fed by the core unit while shuttling incessantly and are interwoven with each other while passing through the two intersection points during the incessant shuttling motion, thereby wrapping a multi-convolutional braided layer around the core strand to complete a rope. Each convolution of the braided layer has two crossing points, which increases the practicability of the rope.