Patents by Inventor Ming-Chin Chien
Ming-Chin Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921434Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: GrantFiled: December 15, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11740563Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: GrantFiled: February 22, 2022Date of Patent: August 29, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20230124211Abstract: An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20220179326Abstract: A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 11256179Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: GrantFiled: October 22, 2019Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 10976672Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: GrantFiled: April 29, 2019Date of Patent: April 13, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Patent number: 10685846Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: GrantFiled: May 16, 2014Date of Patent: June 16, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chung, Kuo-Chang Kau, Jeng-Horng Chen
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Publication number: 20200050118Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: ApplicationFiled: October 22, 2019Publication date: February 13, 2020Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Patent number: 10459352Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: GrantFiled: August 31, 2015Date of Patent: October 29, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20190250522Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Inventors: Jui-Ching WU, Jeng-Horng CHEN, Chia-Chen CHEN, Shu-Hao CHANG, Shang-Chieh CHIEN, Ming-Chin CHIEN, Anthony YEN
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Patent number: 10274838Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: GrantFiled: May 22, 2013Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Patent number: 10067418Abstract: A method of removing particles from a surface of a reticle is disclosed. The reticle is placed in a carrier, a source gas is flowed into the carrier, and a plasma is generated within the carrier. Particles are then removed from a surface of the reticle using the generated plasma. A system of removing particles from a surface includes a carrier configured to house a reticle, a reticle stocker including the carrier, a power supply configured to apply a potential between an inner cover and an inner baseplate of the carrier, and a gas source configured to flow a gas into the carrier. A plasma may be generated within the carrier, and particles can be removed from a surface of the reticle using the generated plasma. An acoustic energy source configured to agitate at least one of the source gas and the generated plasma may be provided to facilitate particle removal using an agitated plasma.Type: GrantFiled: May 12, 2014Date of Patent: September 4, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hao Chang, Chi-Lun Lu, Shang-Chieh Chien, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen, Chieh-Jen Cheng, Chia-Chen Chen
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Patent number: 9665007Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: GrantFiled: August 29, 2016Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20170060005Abstract: A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Shu-Hao Chang, Norman Chen, Jeng-Horng Chen, Kuo-Chang Kau, Ming-Chin Chien, Shang-Chieh Chien, Anthony Yen, Kevin Huang
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Publication number: 20160370705Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: ApplicationFiled: August 29, 2016Publication date: December 22, 2016Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Patent number: 9429858Abstract: An EUV collector is rotated between or during operations of an EUV photolithography system. Rotating the EUV collector causes contamination to distribute more evenly over the collector's surface. This reduces the rate at which the EUV photolithography system loses image fidelity with increasing contamination and thereby increases the collector lifetime. Rotating the collector during operation of the EUV photolithography system can induce convection and reduce the contamination rate. By rotating the collector at sufficient speed, some contaminating debris can be removed through the action of centrifugal force.Type: GrantFiled: September 24, 2013Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Tsung-Yu Chen, Tzu-Hsiang Chen, Ming-Chin Chien, Chia-Chen Chen, Jeng-Horng Chen
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Publication number: 20160054664Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.Type: ApplicationFiled: May 22, 2013Publication date: February 25, 2016Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
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Publication number: 20150332922Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. An inverse mask is provided. A sacrificial layer is deposited over a substrate. A patterned photoresist layer is formed over the sacrificial layer using the inverse mask. The sacrificial layer is then etched through the patterned photoresist layer to form a patterned sacrificial layer. A hard mask layer is deposited over the patterned sacrificial layer. The patterned sacrificial layer is then removed to form a second pattern on the hard mask layer.Type: ApplicationFiled: May 16, 2014Publication date: November 19, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chin Chien, Jui-Ching Wu, Shu-Hao Chang, Shang-Chieh Chien, Jen-Yang Chaung, Kuo-Chang Kau, Jeng-Horng Chen
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Publication number: 20150323862Abstract: A method of removing particles from a surface of a reticle is disclosed. The reticle is placed in a carrier, a source gas is flowed into the carrier, and a plasma is generated within the carrier. Particles are then removed from a surface of the reticle using the generated plasma. A system of removing particles from a surface includes a carrier configured to house a reticle, a reticle stocker including the carrier, a power supply configured to apply a potential between an inner cover and an inner baseplate of the carrier, and a gas source configured to flow a gas into the carrier. A plasma may be generated within the carrier, and particles can be removed from a surface of the reticle using the generated plasma. An acoustic energy source configured to agitate at least one of the source gas and the generated plasma may be provided to facilitate particle removal using an agitated plasma.Type: ApplicationFiled: May 12, 2014Publication date: November 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Hao Chang, Chi-Lun Lu, Shang-Chieh Chien, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen, Chieh-Jen Cheng, Chia-Chen Chen
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Patent number: 9140987Abstract: A method of reducing resist outgassing for EUV lithography is disclosed. The method includes forming a material layer over a substrate wherein a top surface of the material layer contains a certain concentration of a quencher or a base. The method further includes forming a resist layer over the top surface of the material layer and exposing the resist layer to a EUV radiation for patterning. The quencher or the base underneath the resist layer acts to suppress resist outgassing during the EUV exposure. The material layer itself may serve as a hard mask layer or an anti-reflection layer for the patterning process, in addition to being the carrier of the quencher or the base. The method can be used in other types of lithography, such as e-beam lithography, for reducing resist outgassing.Type: GrantFiled: February 21, 2014Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Chieh Chien, Shu-Hao Chang, Hsiang-Yu Chou, Ming-Chin Chien, Jui-Ching Wu, Jeng-Horng Chen