Abstract: Methods of forming integrated circuits forming a first conductive structure at a first level of the integrated circuit, forming a first conductor at a second level of the integrated circuit to be in physical and electrical contact with the first conductive structure, forming a second conductor at the second level to be in physical and electrical contact with the first conductive structure and to be parallel to the first conductor, forming a third conductor at the second level to be isolated from the first conductive structure and to be parallel to the first conductor and to the second conductor, and forming a second conductive structure at a third level of the integrated circuit to be in physical and electrical contact with the second conductor and with the third conductor, wherein the second level is between the first level and the third level.

Abstract: Integrated circuits include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

Abstract: Disclosed herein are novel liquid crystal compounds of formula I: wherein each of the substituents is given the definition as set forth in the Specification and Claims. Also disclosed are liquid crystal media including the novel liquid crystal compounds of formula I, which are suitably applied in an active matrix display device.

Abstract: A liquid crystal composition includes at least one polar compound represented by Formula (I), at least one polar compound represented by Formula (II), at least one compound represented by Formula (III), and at least one compound represented by Formula (IV), in which Formulae (I) to (IV) are as defined herein.

Abstract: Integrated circuits include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

Abstract: Methods of forming integrated circuits forming a first conductive structure at a first level of the integrated circuit, forming a first conductor at a second level of the integrated circuit to be in physical and electrical contact with the first conductive structure, forming a second conductor at the second level to be in physical and electrical contact with the first conductive structure and to be parallel to the first conductor, forming a third conductor at the second level to be isolated from the first conductive structure and to be parallel to the first conductor and to the second conductor, and forming a second conductive structure at a third level of the integrated circuit to be in physical and electrical contact with the second conductor and with the third conductor, wherein the second level is between the first level and the third level.

Abstract: Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: Integrated circuits, as well as methods of their formation, include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

Abstract: An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass.

Abstract: An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass.

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract: Microlithography masks are disclosed, such as those that include one or more image reversal assist features disposed between at least two primary mask features. The one or more image reversal assist features may be defined by a patterned relatively non-transparent material on a mask substrate. Microlithography systems include such masks. Methods of forming microlithography masks are also disclosed, such as those that include patterning a relatively non-transparent material on a mask substrate to form at least one image reversal assist feature located between at least two primary features.