Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a layer of first material over the substrate, providing a layer of photoresist over the layer of first material, patterning and defining the photoresist layer to form at least one photoresist structure having at least one substantially vertical sidewall and one substantially horizontal surface, wherein a surface of the at least one substantially vertical sidewall is in the shape of a standing wave, and depositing a layer of polymer over the patterned and defined photoresist layer, wherein the polymer layer is substantially conformal and covers the at least one substantially vertical sidewall and one substantially horizontal surface, and wherein the polymer layer covers the standing wave on the surface of the at least one substantially vertical sidewall to form a substantially smooth profile.

Abstract: A passivation layer is deposited onto the surface of a substrate followed by deposition of a polymer layer, through the application of a plasma enhanced chemical vapor deposition process, in which the substrate is placed on a chuck within a reaction chamber and fluorocarbon gas is introduced into the reaction chamber under the influence of at least one plasma source. The fluorocarbon gas can be a CFX gas. The at least one plasma source can include a first plasma source that ionizes the fluorocarbon gas by applying RF plasma energy, and a second plasma source that applies a near-zero self-bias to the substrate at an RF frequency during deposition of the passivation layer and a greater bias during deposition of the polymer layer. The passivation layer is deposited prior to the polymer layer to protect the surface of the substrate from damage during the deposition of the polymer layer.

Abstract: A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features.

Abstract: A method for manufacturing a photomask is provided. A transparent substrate is provided and a mask layer is formed thereon. A resist layer is formed on the mask layer and then patterned and defined to define a critical dimension of the photomask. A third layer is deposited over the patterned and defined resist layer to decrease the critical dimension of the photomask. And the third layer and the mask layer are etched afterwards.

Abstract: A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

Abstract: A semiconductor manufacturing method that includes providing a substrate, providing a layer of semiconductor material over the substrate, providing a layer of photoresist over the semiconductor material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of semiconductor material.

Abstract: An operating method of a semiconductor etcher includes three steps. The first step is to provide a first power for shortening a warm-up time of the etcher. The second step is to provide a second power, which is lower than the first power, to perform an etching process. The third step is to provide a third power, which is between the first and second power, for cleaning the etcher.

Abstract: The present invention is to utilize chemical dry etching technique to form a rounded corner in a shallow trench isolation process. After finishing the etching of the shallow trench, the present invention utilizes an isotropic etching step, which is a chemical dry etching step of a high silicon nitride to silicon etching selectivity, to pullback the silicon nitride layer to expose a silicon top corner. Then, the present invention utilizes an isotropic etching step, which is a chemical dry etching step of a high silicon to silicon nitride etching selectivity, to make the corner rounded to obtain a rounded corner of the shallow trench isolation structure. The present invention can avoid the formation of wrap rounding of the corner and prevent the formation of the short circuit or extraordinary electric behavior between adjacent devices and supply for performing following processes.

Abstract: An apparatus for cleaning a semiconductor wafer is disclosed to substantially improve the efficiency of the cleaning process, and reduce the quantity of cleaning solvent used. The apparatus includes a rotating table for supporting the wafer, a rotation device to rotate the rotation table, a movable or stationary curved-slab for scrubbing the surface of the wafer efficiently, a cleaning nozzle for applying a cleaning solvent or stripper on the surface of the wafer, and a resistance wall for preventing the cleaning solvent spun out from the wafer to pollute the cleaning room.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a first layer over the substrate, providing a protection layer over the first layer, providing a layer of photoresist over the protection layer, patterning and defining the photoresist layer to form at least one photoresist structure having at least one substantially vertical sidewall and one substantially horizontal top, depositing a photo-insensitive material over the at least one photoresist structure and the protection layer with a chemical-vapor deposition process having at least one reactive gas, wherein an amount of the photo-insensitive material deposited on the top of the photoresist structure is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the photoresist structure, and wherein the protection layer is non-reactive with the at least one reactive gas, and anisotropically etching the protection layer and the layer to be etched.

Abstract: A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

Abstract: A method of etching that can increase the etching selectivity between the dielectric material and silicon in a polysilicon etching apparatus is disclosed. The present invention is a dry etching method, and the gas recipe of the polysilicon plasma etching apparatus is adjusted to serve carbon tetrafluoride (CF4)/fluoromethane (CHxFy; x=2, y=2 or x=1, y=3)/Oxygen (O2) as the reactive gas. Therefore, the dielectric material layer and the polysilicon layer both can be etched in a polysilicon plasma etching apparatus, and the etching selectivity between the dielectric material layer and silicon can be enhanced greatly, so that a straight etching profile and a stable chamber environment can be obtained.

Abstract: The present invention generally relates to provide a fabrication method for forming a rounded corner of a contact window or a via by using a two-step light etching technique. In the present invention, after the etching process to form the contact window or the via, an object of the invention is to utilize oxygen plasma and fluorocarbon plasma of the two-step light etching technique to produce the rounded corner of the window or via so as this rounded opening profile of the contact window or the via can supply for following metal-filling processes.

Abstract: A plasma etching gas, suitable for etching the silicon layer in a silicon oxide etching device. The plasma etching gas can be a fluoroalkane gas, such as fully fluoro-substituted alkane gas and a partially fluoro-substituted alkane gas, an argon gas or a nitrogen gas. The ratio of the partially fluoro-substituted alkane to the fully fluoro-substituted alkane in the plasma etching gas is about 3/1 to about 15/1.

Abstract: This invention provides a method for chamber conditioning with deposition mode. The method includes performing organic gas introduced constantly into a chamber, wherein said organic gas comprises halogen. Adhesive polymers are formed from said organic gas and particles in the chamber, and deposited onto the wall of the chamber to form heavy polymers subsequently. It is necessary to make a similar chamber condition for manufacturing every batch of wafer. In other words, the development of a non-ignored pollution problem, which is increasing with batches of the manufacturing of wafers will not occur. By using said method of deposition mode, it is speedily and easy to decrease the amount of particles in the chamber for the requirement for wafer manufacturing.

Abstract: A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

Abstract: The present invention provides a vertical batch type wafer cleaning apparatus comprising a wafer bearing apparatus in a cleaning tank. The wafer bearing apparatus comprises three parallel upstanding racks and a plurality of wafer shelves arranged up and down between the three racks. Three deflections are uniformly formed at edge of each of the wafer shelves. The three racks have two cover bodies at two ends thereof to connect two rotators. The wafer bearing apparatus is driven to rotate by synchronous rotation of the two rotators. A flow distributor is provided in the cleaning tank to connect an output pipe of the cleaning solution supply tank so that cleaning solution can be distributed and transferred to between the wafer shelves. Two filter pipes are provided between the cleaning tank and the cleaning solution supply tank to let cleaning solution be used in recirculating way. The present invention has advantages of enhanced cleaning efficiency and reduced cost.