Abstract: A semiconductor package structure includes first via structures formed through a core substrate. The structure also includes an interposer embedded in the core substrate between the first via structures. The interposer includes second via structures formed through an interposer substrate. The structure also includes a first redistribution layer structure formed over the core substrate. The structure also includes a second redistribution layer structure formed under the core substrate. The structure also includes a first encapsulating layer formed between a sidewall of the interposer and a sidewall of the core substrate.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.

Abstract: A method for forming a package structure is provided. The method includes etching a top surface of a substrate to form a cavity. The substrate includes thermal vias directly under a bottom surface of the cavity. The method also includes forming at least one first electronic device in the cavity of the substrate. The first electronic device is thermally coupled to the thermal vias. The method further includes forming an encapsulating material in the cavity, so that the encapsulating material extends along sidewalls of the first electronic device and covers a surface of the first electronic device opposite the bottom surface of the cavity. In Addition, the method includes forming an insulating layer having an RDL structure over the encapsulating material. The RDL structure is electrically connected to the first electronic device.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a package layer surrounding the integrated circuit die. The package structure also includes a redistribution structure over the package layer and electrically connected to the integrated circuit die. The redistribution structure includes a passivation layer and a conductive layer formed in the passivation layer. The integrated circuit die further includes a connector formed over the conductive layer and covered a top surface of the passivation layer. In addition, a bottom surface of the connector and a top surface of the connector are both wider than a neck portion of the connector.

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method includes forming a reconstructed package substrate, which includes placing a plurality of substrate blocks over a carrier, encapsulating the plurality of substrate blocks in an encapsulant, planarizing the encapsulant and the plurality of substrate blocks to reveal redistribution lines in the plurality of substrate blocks, and forming a redistribution structure overlapping both of the plurality of substrate blocks and encapsulant. A package component is bonded over the reconstructed package substrate.

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.