Patents by Inventor Ming-Da Hsieh
Ming-Da Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 8883648Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.Type: GrantFiled: September 9, 2013Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Ming-Da Hsieh, Yu-Tsung Lai, Hsuan-Hsu Chen
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Patent number: 8323877Abstract: A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.Type: GrantFiled: November 16, 2010Date of Patent: December 4, 2012Assignee: United Microelectronics Corp.Inventors: Ming-Da Hsieh, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Publication number: 20120289043Abstract: A method for fabricating a damascene trench structure, wherein the method comprises steps as follows: A semiconductor structure having an inner layer dielectric (ILD) and a patterned hard mask stacked in sequence is firstly provided, in which a trench extends from the patterned hard mask downwards into the ILD. Subsequently, the patterned hard mask is etched in an atmosphere essentially consisting of nitrogen (N2) and carbon-fluoride compositions (CxFy).Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Da HSIEH, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Publication number: 20120122035Abstract: A patterning method and a method for fabricating a dual damascene opening are described, wherein the patterning method includes following steps. An organic layer, a silicon-containing mask layer and a patterned photoresist layer are formed on a material layer in sequence. The silicon-containing mask layer is removed using the patterned photoresist layer as a mask. A reactive gas is used for conducting an etching step so as to remove the organic layer with the silicon-containing mask layer as a mask, wherein the reactive gas contains no oxygen species. The material layer is removed using the organic layer as a mask, so that an opening is formed in the material layer. The organic layer is then removed.Type: ApplicationFiled: November 16, 2010Publication date: May 17, 2012Applicant: United Microelectronics Corp.Inventors: MING-DA HSIEH, Yu-Tsung Lai, Jiunn-Hsiung Liao
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Patent number: 8137472Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.Type: GrantFiled: June 16, 2011Date of Patent: March 20, 2012Assignee: United Microelectronics Corp.Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20110244678Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water. The semiconductor process can reduce the possibility of having an incomplete turning on, a leakage or a short, so that the yield of the product is increased.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Hsiao LEE, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20110130008Abstract: A method to control a critical dimension is disclosed. First, a material layer and a composite patterned layer covering the material layer are provided. The composite patterned layer has a pattern defining a first critical dimension. Later, an etching gas is used to perform an etching step to etch the composite patterned layer and a pattern-transferring step is carried out so that thereby the underlying material layer has a transferred pattern with a second critical dimension which is substantially smaller than the first critical dimension.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Inventors: Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao
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Publication number: 20100105205Abstract: A semiconductor process is provided. First, a metal layer, a dielectric layer and a patterned hard mask layer are sequentially formed on a substrate. Thereafter, a portion of the dielectric layer is removed to form an opening exposing the metal layer. Afterwards, a cleaning solution is used to clean the opening. The cleaning solution includes a triazole compound with a content of 0.00275 to 3 wt %, sulfuric acid with a content of 1 to 10 wt %, hydrofluoric acid with a content of 1 to 200 ppm and water.Type: ApplicationFiled: October 27, 2008Publication date: April 29, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chang-Hsiao Lee, Shih-Fang Tzou, Ming-Da Hsieh, Yu-Tsung Lai, Jyh-Cherng Yau, Jiunn-Hsiung Liao