Abstract: The present invention comprises a footrest with a poking rod; a bumper with an embedding hole is formed on the footrest; a latch member having two bent latch plates, each latch plate having a latch groove with a corresponding concave neck disposed inwardly, and a corresponding concave latch fork inwardly disposed, a latch wing outwardly disposed is formed on the latch groove; a corresponding outwardly protruded extension section is defined under the latch groove; such that the poking rod is clipped by the two plates of the latch member, and engaged by the latch fork. The footrest with the latch member and the poking rod are fully embedded and inserted into the embedding hole on the base of the bumper and secured into a fixed position.

Abstract: Methods and vectors (both DNA and retroviral) are provided for the construction of a Library of mutated cells. The Library will preferably contain mutations in essentially all genes present in the genome of the cells. The nature of the Library and the vectors allow for methods of screening for mutations in specific genes, and for gathering nucleotide sequence data from each mutated gene to provide a database of tagged gene sequences. Such a database provides a means to access the individual mutant cell clones contained in the Library. The invention includes the described Library, methods of making the same, and vectors used to construct the Library. Methods are also provided for accessing individual parts of the Library either by sequence or by pooling and screening. The invention also provides for the generation of non-human transgenic animals which are mutant for specific genes as isolated and generated from the cells of the Library.

Abstract: The present invention makes use of an opening of a latch cover opening to engage the first loose leaf with the second loose leaf at a pivotal opening with a diameter smaller than the opening of the latch cover of the first loose leaf, and the latch cover of the first loose leaf is located between the two axle covers of the second loose leaf after they are coupled. Therefore, the two will not be separated from each other in the front-rear direction easily, so that the first and second loose leaves can be removed and assembled, and fixed securely after the assembling.

Abstract: In the present invention, a first set of latch members and a second set of latch members are disposed on a wheel cover; wherein the first set of latch members encloses a first circular area with a first diameter D, the second set of latch members encloses a second circular area with a second diameter d, and the first diameter D is larger than the second diameter d, such that the wheel cover uses different sets of latch members to enclose areas of different diameters and fits the installation of different sized wheels.

Abstract: A chemical vapor deposition (CVD) method for forming a microelectronic layer within a microelectronic product employs a wetting material treatment of a substrate upon which is formed the microelectronic layer. The wetting material treatment provides for an attenuated incubation or induction time when forming the microelectronic layer, particularly within the context of a digital CVD method, such as an atomic layer CVD method. The microelectronic layer is thus formed with enhanced manufacturability.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT<10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT<1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A rope tie has a cylindrical housing contiguous to a base, with a first bore, a second bore, and a shoulder section contained in the housing and a first groove and a second groove inset along the second bore. A post is movably disposed in the base and consists of a first columnar section, a second columnar section, and a second shoulder section. A spring is seated between the second shoulder section and the first shoulder section, a check section is situated at one extremity of the post, and a hitch hole is formed through the first columnar section. As such, the check section is capable of engaging the first groove or the second groove, thereby enabling the re-positioning of the post.

Abstract: Novel methods for improving the within-wafer uniformity of a gate oxide layer on a semiconductor wafer substrate. According to a first embodiment, a gate oxide layer is formed on a wafer using conventional oxidation parameters and equipment. Next, the edge-thick gate oxide layer is nitridated using a center-thick plasma nitridation profile to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer. According to a second embodiment, the wafer substrate is first nitridated and then oxidized to form the gate oxide layer. The nitrogen incorporated into the wafer surface during the nitridation step retards oxidation of the wafer at the wafer edge to enhance uniformity in thickness of the gate oxide layer between the center region and the edge or peripheral regions of the wafer.

Abstract: A method of forming dual gate dielectric layers that is extendable to satisfying requirements for 50 nm and 70 nm technology nodes is described. A substrate is provided with STI regions that separate device areas. An interfacial layer and a high k dielectric layer are sequentially deposited on the substrate. The two layers are removed over one device area and an ultra thin silicon oxynitride layer with an EOT <10 nm is grown on the exposed device area. The high k dielectric layer is annealed during growth of the SiON dielectric layer. The high k dielectric layer is formed from a metal oxide or its silicate or aluminate and enables a low power device to be fabricated with an EOT <1.8 nm with a suppressed leakage current. The method is compatible with a dual or triple oxide thickness process when forming multiple gates.

Abstract: A steel wheel with a retaining base. The steel wheel includes a bearing, a turning disc, an axle disposed on the turning disc and pivotally coupled to the bearing on the retaining base. A wing plate is defined on the turning disc so that the wing plate rotates independently from the wheel cover when the vehicle is moving.

Abstract: A wheel cover. The wheel cover includes engraved holes with special shapes on a circular disc of the wheel cover, latch members on the backside of the wheel cover, and the latch members define a diameter of an area on the wheel cover for embedding the steel wheel. A turning disc is disposed on the wheel cover. An axle is disposed on the axle and pivotally coupled to a bearing on the wheel cover. A wing plate is defined on the turning disc, and the wing plate rotates independently from the wheel cover when the vehicle is moving.

Abstract: A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A method of making a semiconductor device having a silicon dioxide based gate with improved dielectric properties including providing a silicon based substrate having active areas defined therein. Thermally growing a silicon dioxide based gate from the silicon based substrate. Nitriding the silicon dioxide based gate to provide a nitrided silicon dioxide based gate and to increase the dielectric constant of the silicon dioxide based gate without substantially increasing thickness of the silicon dioxide based gate.

Abstract: A new method is provided for the creation of a layer of gate dielectric for gate electrodes having deep sub-micron dimensions. The inventions provides three embodiments of cleaning the backside of a surface that is being processed for the creation of a gate electrode over the surface thereof. Solutions of Hydrofluoric acid (HF) with different concentrations or other cleaning agents are used for the cleaning of the backside of the substrate. The steps of cleaning the backside of the substrate can be performed at different intervals of creating a layer of high-k gate dielectric and the overlying layer of polysilicon, the process of backside cleaning can be applied more than once in order to remove all residue of high-k dielectric and polysilicon from the backside of the substrate.