Abstract: A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

Abstract: An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver which is connected to the set of data lines and is configured to receive a flip-refresh control signal. The read-write driver has a catch circuit configured to store a first bit value related to a stored bit value in a selected memory cell. The read-write driver is configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.

Abstract: A transistor device includes a first source/drain region and a second source/drain region spaced apart from each other; a channel layer electrically connected to the first and second source/drain regions; a gate insulator layer; a gate electrode isolated from the channel layer by the gate insulator layer; and a UV-attenuating layer disposed on the channel layer to protect the channel layer from characteristic degradation caused by UV light.