Patents by Inventor Ming-Ho Tsai
Ming-Ho Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367396Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.Type: ApplicationFiled: July 26, 2022Publication date: November 17, 2022Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Patent number: 11469198Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.Type: GrantFiled: March 14, 2019Date of Patent: October 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Ho Tsai, Jyun-Hong Chen, Chun-Chen Liu, Yu-Nu Hsu, Peng-Ren Chen, Wen-Hao Cheng, Chi-Ming Tsai
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Patent number: 11262658Abstract: A photomask includes a transparent substrate and a shielding pattern disposed on the transparent substrate. The shielding pattern includes shielding island structures. The shielding island structures are separated from and spaced apart from one another by dividing lanes. The dividing lanes expose the underlying transparent substrate. The photomask is configured for a light of a wavelength, and the dividing lanes reduce or hinder a transmission of the light of the wavelength.Type: GrantFiled: April 28, 2020Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Yuan Chang, Chih-Chiang Tu, Ming-Ho Tsai, Ching-Hung Lai
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Publication number: 20210333705Abstract: A photomask includes a transparent substrate and a shielding pattern disposed on the transparent substrate. The shielding pattern includes shielding island structures. The shielding island structures are separated from and spaced apart from one another by dividing lanes. The dividing lanes expose the underlying transparent substrate. The photomask is configured for a light of a wavelength, and the dividing lanes reduce or hinder a transmission of the light of the wavelength.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Yuan Chang, Chih-Chiang Tu, Ming-Ho Tsai, Ching-Hung Lai
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Publication number: 20200020655Abstract: A semiconductor device manufacturing method including: simultaneously forming a plurality of conductive bumps respectively on a plurality of formation sites by adjusting a forming factor in accordance with an environmental density associated with each formation site; wherein the plurality of conductive bumps including an inter-bump height uniformity smaller than a value, and the environmental density is determined by a number of neighboring formation sites around each formation site in a predetermined range.Type: ApplicationFiled: March 14, 2019Publication date: January 16, 2020Inventors: MING-HO TSAI, JYUN-HONG CHEN, CHUN-CHEN LIU, YU-NU HSU, PENG-REN CHEN, WEN-HAO CHENG, CHI-MING TSAI
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Patent number: 10274817Abstract: A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 ?m2 to 60000 ?m2. The second pattern has an area of 0.16 ?m2 to 60000 ?m2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.Type: GrantFiled: March 31, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hung Lai, Chih-Chung Huang, Chih-Chiang Tu, Chung-Hung Lin, Chi-Ming Tsai, Ming-Ho Tsai
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Publication number: 20180284595Abstract: A mask includes a transparent substrate, a first pattern, a second pattern, and a sub-resolution auxiliary feature. The first pattern and the second pattern are over the transparent substrate. The first pattern has an area of 0.16 ?m2 to 60000 ?m2. The second pattern has an area of 0.16 ?m2 to 60000 ?m2. The sub-resolution auxiliary feature is over the transparent substrate and connects the first pattern and the second pattern.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Hung Lai, Chih-Chung Huang, Chih-Chiang Tu, Chung-Hung Lin, Chi-Ming Tsai, Ming-Ho Tsai
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Patent number: 9230867Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.Type: GrantFiled: May 23, 2014Date of Patent: January 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dong-Hsu Cheng, Ming-Ho Tsai, Chih-Chung Huang, Yung-Hsiang Chen, Jyun-Hong Chen
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Publication number: 20150316861Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Inventors: Dong-Hsu Cheng, Chun-Jen Chen, Jim Liang, Yung-Hsiang Chen, Jun-Hua Chen, Ming-Ho Tsai
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Patent number: 9081293Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.Type: GrantFiled: October 17, 2013Date of Patent: July 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dong-Hsu Cheng, Chun-Jen Chen, Ming-Ho Tsai, Jim Liang, Yung-Hsiang Chen, Jun-Hua Chen
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Publication number: 20140272717Abstract: A method of exposing a wafer substrate includes receiving an integrated circuit (IC) design layout defining a pattern; determining a temperature profile of a mask based on the IC design layout, the pattern being formed on the mask; calculating a pre-corrected overlay shift for the mask based on the calculated temperature profile; and exposing a resist layer coated on a substrate using the mask with overlay compensation based on the pre-corrected overlay shift.Type: ApplicationFiled: October 17, 2013Publication date: September 18, 2014Inventors: Dong-Hsu Cheng, Chun-Jen Chen, Ming-Ho Tsai, Jim Liang, Yung-Hsiang Chen, Jun-Hua Chen
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Publication number: 20140256067Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dong-Hsu Cheng, Ming-Ho Tsai, Chih-Chung Huang, Yung- Hsiang Chen, Jyun-Hong Chen
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Patent number: 8736084Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.Type: GrantFiled: December 8, 2011Date of Patent: May 27, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dong-Hsu Cheng, Ming-Ho Tsai, Chih-Chung Huang, Yung-Hsiang Chen, Jyun-Hong Chen
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Publication number: 20130147066Abstract: The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Dong-Hsu Cheng, Ming-Ho Tsai, Chih-Chung Huang, Yung-Hsiang Chen, Chun-Hung Chen