Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A method of manufacturing a buried contact is disclosed, wherein a thin silicon oxide layer is formed on the silicon substrate. The thin oxide functions as a gate dielectric. Subsequently, a thin first polysilicon layer is formed on the thin silicon oxide layer. Then, a buried contact opening is defined by a first photoresist mask. The portion of the thin polysilicon layer exposed through the first photoresist mask and the thin silicon oxide layer underneath the exposed thin polysilicon are anisotropically etched to forma buried contact hole. An ion implantation is performed into the substrate throughout the buried contact hole to form an N+region. The first photoresist mask is removed and a layer of undoped silicon oxide is deposited on the entire surface. An anisotropic etching is used to etch the undoped silicon oxide. The etching depth can be controlled by this process. Residual amounts of undoped silicon oxide are retained on the vertical edges of the buried contact hole to act as spacers.

Abstract: A semiconductor cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.

Abstract: In a CMOS device uses a thin oxide film as a gate dielectric film, gate electrode plasma etching frequently induces gate dielectric damage. This invention discloses a process which can form a damage free gate dielectric even though there is plasma nonuniformity during gate electrode etching. In this invention, a thin polysilicon layer is formed on the gate dielectric (gate oxide) layer and a thin oxide layer (not gate oxide) is formed on the thin polysilicon layer. The thin oxide layer (not gate oxide) is then patterned and etched to expose portions of the thin polysilicon layer. A thick polysilicon layer used to form the gate electrode is subsequently deposited. The thick polysilicon layer contacts the exposed portion of the underlying thin polysilicon layer, but is otherwise separated from the thin polysilicon layer by the thin oxide. The thin polysilicon layer is patterned and etched using a plasma etching process. The thin oxide (not the gate oxide) acts as an etching stop.

Abstract: A method for forming a MOSFET device, having Lightly Doped Drain structures with reduced primary crystalline defect damage wherein a semiconductor structure is provided having a thin silicon oxide layer on a silicon substrate, a polysilicon layer formed on the silicon oxide layer, and a photoresist mask formed on the polysilicon layer. The mask is patterned to form two narrow slit openings through which the polysilicon layer is exposed. The exposed polysilicon is anisotropically etched to define a gate region between the two slits. A first ion implantation forms two lightly doped regions in the substrate on either side of the gate region. The ion implantation takes place through the slits so that the implanted regions in the substrate are narrow. This limits the region of the substrate in which there is primary crystalline defect damage. The first photoresist mask layer is removed.

Abstract: A method of forming a gate on a silicon substrate with a preformed film of gate oxide. A polysilicon layer is formed on the gate oxide. A slit is then formed in a predetermined area of the polysilicon layer. A masking layer is formed on the surface of the polysilicon layer surrounded by the slit. Exposed polysilicon is then removed, and the masking layer is removed.

Abstract: A process for fabricating load resistors for memory cell units of semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device with a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, the first dielectric layer having opening vias connecting to the gate electrode of the gate structure and a source/drain region. A polysilicon layer is then deposited. The polysilicon layer is then patterned by etching to form a discontinuity between the gate electrode and one of the source/drain regions. An oxidation resistant layer is formed and patterned for exposing regions of the polysilicon layer designated for the formation of the load resistors. An oxide layer is formed over the surface of the exposed portions of the polysilicon layer, so that the thickness of the designated regions of the polysilicon layer underneath the oxide layer is reduced.

Abstract: A process for fabricating load resistors for memory cell units of a semiconductor SRAM device. The process includes providing a silicon substrate containing an intermediate semiconductor device having a gate structure and source/drain regions for a transistor of the cell unit. A first dielectric layer is then formed over the surface of the silicon substrate, wherein the first dielectric layer has an opening via exposing the gate electrode of the gate structure. A polysilicon layer is then deposited and patterned for forming a first connector in the via, at least one dummy structure on the first dielectric layer, and a second connector. A second dielectric layer is then formed to have two further vias respectively exposing the first and second connectors. A polysilicon load resistor is formed and coupled electrically to the first and second connectors and extends over the surface of the at least one dummy structure so as to have an elongated length.

Abstract: A manufacturing process for a CMOS cell with a buried contact uses highly selective etching techniques in combination with a thin oxide etching stop to prevent damage to the buried contact during the etching process. A cavity is formed in the oxide layer between the buried contact and its adjacent interconnect polysilicon element. A self-aligning silicide process (salicide) is used to coat the interconnect polysilicon, the cavity, and the buried contact, to form a continuous electrical connection between the interconnect polysilicon and the buried contact.

Abstract: A process of forming contact holes having tapered sidewalls is accomplished by establishing sidewall spacers in the contact hole area. A photo-resist layer is formed on top of a semiconductor device having a substrate with doped regions, a polysilicon layer and a multi-layer insulating structure. The photo-resist layer has openings defining area slightly larger than the sizes of the actual contact holes. The multi-layer insulating structure is anisotropically eteched to remove one half of the thickness in the opening area and a void with vertical sidewall is formed in the insulating structure. After etching, the photo-resist layer is removed and a temporary insulating layer having the same composition as the top layer of the multi-layer insulating structure is deposited uniformly over the surface of the multi-layer insulating structure. The temporary insulating layer is etched and removed by anisotropically etching process.