Patents by Inventor Ming-Hsiang Hsueh
Ming-Hsiang Hsueh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
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Patent number: 11010886Abstract: Systems and methods for automatic correction of drift between inspection and design for massive pattern searching are disclosed herein. Defects are identified in a scan of a wafer. The defects are associated with tool coordinates. An SEM review tool captures centered images of the defects. The SEM review tool is aligned with the wafer using design polygons in an imported design file. Design coordinates are exported and used to define patterns of interest and identifying locations of those patterns of interest.Type: GrantFiled: May 12, 2017Date of Patent: May 18, 2021Assignee: KLA-Tencor CorporationInventors: Chi-Yuan Tseng, Ming-Hsiang Hsueh
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Publication number: 20170337673Abstract: Systems and methods for automatic correction of drift between inspection and design for massive pattern searching are disclosed herein. Defects are identified in a scan of a wafer. The defects are associated with tool coordinates. An SEM review tool captures centered images of the defects. The SEM review tool is aligned with the wafer using design polygons in an imported design file. Design coordinates are exported and used to define patterns of interest and identifying locations of those patterns of interest.Type: ApplicationFiled: May 12, 2017Publication date: November 23, 2017Inventors: Chi-Yuan Tseng, Ming-Hsiang Hsueh
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Patent number: 7932507Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.Type: GrantFiled: March 19, 2010Date of Patent: April 26, 2011Assignees: International Business Machines Corporation, Qimonda North America Corp., Macronix International Co., Ltd.Inventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
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Patent number: 7795088Abstract: A method for manufacturing memory cells is provided. First, a substrate is provided, wherein a liner layer and a material layer have already been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the substrate. Then, the patterned mask layer is trimmed. Subsequently, a portion of the material layer, a portion of the liner layer and a portion of the substrate are removed by using the patterned mask layer as a mask to define a plurality of fin-structures in the substrate. Afterward, the patterned mask layer is removed and a plurality of isolation structures among the fin structures is formed. The surface of the isolation structures is lower than that of the fin structures. Following that, charge trapping structures are formed on the substrate, covering the fin structures. Succeeding, a portion of the charge trapping structures is removed to expose the material layer. Then, the treatment process turns the material layer into a protection layer.Type: GrantFiled: May 25, 2007Date of Patent: September 14, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Tzu-Hsuan Hsu, Ming-Hsiang Hsueh, Yen-Hao Shih, Chia-Wei Wu
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Patent number: 7785963Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.Type: GrantFiled: February 22, 2008Date of Patent: August 31, 2010Assignee: MACRONIX International Co., Ltd.Inventors: Ming-Hsiang Hsueh, Yen-Hao Shih, Erh-Kun Lai
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Patent number: 7772068Abstract: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.Type: GrantFiled: August 30, 2006Date of Patent: August 10, 2010Assignee: Macronix International Co., Ltd.Inventor: Ming-Hsiang Hsueh
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Publication number: 20100193763Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.Type: ApplicationFiled: March 19, 2010Publication date: August 5, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
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Patent number: 7745807Abstract: A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.Type: GrantFiled: July 11, 2007Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
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Patent number: 7593262Abstract: A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.Type: GrantFiled: December 12, 2006Date of Patent: September 22, 2009Assignee: Macronix International Co., Ltd.Inventors: Chao-I Wu, Ming-Hsiang Hsueh
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Publication number: 20090215256Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment.Type: ApplicationFiled: February 22, 2008Publication date: August 27, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Hsiang HSUEH, Yen-Hao SHIH, Erh-Kun LAI
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Publication number: 20090130835Abstract: A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T-shape, a U-shape, a trapezoid shape, or a double inverted T-shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T-shape, such that a top contour is a non-flat segment.Type: ApplicationFiled: November 16, 2007Publication date: May 21, 2009Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Erh-Kun LAI, Yen-Hao SHIH, Ming-Hsiang HSUEH
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Patent number: 7521321Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.Type: GrantFiled: March 30, 2007Date of Patent: April 21, 2009Assignee: MACRONIX International Co., Ltd.Inventors: Yen-Hao Shih, Ming-Hsiang Hsueh, Erh-Kun Lai, Chia-Wei Wu, Chi-Pin Lu, Jung-Yu Hsieh
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Publication number: 20090014704Abstract: A layer of nanopaiticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.Type: ApplicationFiled: July 11, 2007Publication date: January 15, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chieh-Fang Chen, Shih Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
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Publication number: 20080290397Abstract: A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.Type: ApplicationFiled: May 25, 2007Publication date: November 27, 2008Applicant: MACRONIX International Co., Ltd.Inventors: Tzu-Hsuan Hsu, Ming-Hsiang Hsueh, Yen-Hao Shih, Chia-Wei Wu
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Publication number: 20080165569Abstract: A memory cell comprises a first electrode, a second electrode and a composite material. The composite material electrically couples the first electrode to the second electrode. Moreover, the composite material comprises a phase change material and a resistor material. At least a portion of the phase change material is operative to switch between a substantially crystalline phase and a substantially amorphous phase in response to an application of a switching signal to at least one of the first and second electrodes. In addition, the resistor material has a resistivity lower than that of the phase change material when the phase change material is in the substantially amorphous phase.Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Inventors: Chieh-Fang Chen, Shih-Hung Chen, Yi-Chou Chen, Thomas Happ, Chia Hua Ho, Ming-Hsiang Hsueh, Chung Hon Lam, Hsiang-Lan Lung, Jan Boris Philipp, Simone Raoux
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Publication number: 20080164513Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.Type: ApplicationFiled: March 30, 2007Publication date: July 10, 2008Applicant: Macronix International Co., Ltd.Inventors: Yen-Hao Shih, Ming-Hsiang Hsueh, Erh-Kun Lal, Chia-Wei Wu, Chi-Pin Lu, Jung-Yu Hsieh
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Publication number: 20080137407Abstract: A method for operating memory used for enabling the memory device to have a first threshold voltage or a second threshold voltage is provided. The method includes the following procedures. First, an operating voltage is applied to a gate of the memory device for a first time period, such that the memory device has the first threshold voltage. Next, the same operating voltage is applied to the gate of the memory for a second time period, such that the memory device has a second threshold voltage. The duration of the first time period is different from the duration of the second time period.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Inventors: Chao-I Wu, Ming-Hsiang Hsueh
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Patent number: 7381982Abstract: A chalcogenide memory cell includes a lower electrode, a chalcogenide layer, and an upper electrode. The lower electrode includes a tapered cavity. The chalcogenide layer is formed in the tapered cavity of the lower electrode. One side of the chalcogenide layer is adjacent to the lower electrode. The upper electrode is formed in a second cavity formed by the chalcogenide layer so that the upper electrode substantially fills the second cavity. The upper electrode is adjacent to the other side of the chalcogenide layer. Information is stored and retrieved by passing current between the upper electrode and the lower electrode. The tapered cavity of the lower electrode is formed through anisotropic etching or through sidewall-application. Undesired currents are prevented using an additional dielectric layer or by using an additional conductive layer that forms a p-n junction with the lower electrode.Type: GrantFiled: August 26, 2005Date of Patent: June 3, 2008Assignee: Macronix International Co., Ltd.Inventor: Ming-Hsiang Hsueh
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Publication number: 20080057651Abstract: A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.Type: ApplicationFiled: August 30, 2006Publication date: March 6, 2008Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventor: Ming-Hsiang Hsueh