Abstract: A disease diagnosing method and a disease diagnosing system are provided in the disclosure. The disease diagnosing method includes: obtaining continuous images of a body skin and generating a time domain signal according to an average pixel value of a region of interest in each frame of the continuous images; transforming the time domain signal to a frequency domain signal and combining the time domain signal and the frequency domain signal to a time frequency signal; retrieving multiple first features of a first high dimensional space of the time frequency signal to obtain multiple second features of a second high dimensional space; and use the second features as feature vectors to map to a high dimension feature space, and classifying the second features as one of the multiple categories of a disease corresponding to the region of interest in the body skin according to a hyperplane of the high dimension feature space.

Abstract: An integrated circuit (IC) package includes an interconnect. The interconnect has a connecting tie bar and a die pad. The IC package also includes a die mounted on the die pad of the interconnect. The IC package further includes a wire bond coupled to the die and the connecting tie bar to provide a current path between the die and the connecting tie bar.

Abstract: Some implementations described herein include systems and techniques for fabricating a stacked die product. The systems and techniques include using a supporting fill mixture that includes a combination of types of composite particulates in a lateral gap region of a stack of semiconductor substrates and along a perimeter region of the stack of semiconductor substrates. One type of composite particulate included in the combination may be a relatively smaller size and include a smooth surface, allowing the composite particulate to ingress deep into the lateral gap region. Properties of the supporting fill mixture including the combination of types of composite particulates may control thermally induced stresses during downstream manufacturing to reduce a likelihood of defects in the supporting fill mixture and/or the stack of semiconductor substrates.

Abstract: Disclosed herein is a nanocomposite comprising a core-shell nanoparticle and a core-shell quantum dot. The core-shell nanoparticle comprises a phosphor core, a shell layer, and a cleavable peptide. The core-shell quantum dot comprises a center core, an intermediate layer, an outer layer, a silica layer, and an arginylglycylaspartic acid (RGD) peptide. The core-shell nanoparticle and the core-shell quantum dot are linked to each other via forming a peptide bond between the cleavable peptide and the RGD peptide. Also disclosed are the uses of the nanocomposite in making a diagnosis of tumors.

Abstract: A bioelectronic system for rare cell separation and an application thereof. The bioelectronic system comprises: an electrode; a conductive polymer layer located on a surface of the electrode; a conductive polymer fiber layer located on the surface of the conductive polymer layer not in contact with the electrode; and a rare cell capturing material located the surface of the conductive polymer fiber layer not in contact with the conductive polymer layer. The conductive polymer layer has a thickness of 10-2000 nanometers. A method for rare cell separation can be provided using the bioelectronic system, and includes: introducing a biological fluid containing a rare cell into the bioelectronic system to capture the rare cell; and providing an electrical stimulus by using the electrode of the bioelectronic system to release the captured rare cell.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: In some embodiments, the present disclosure relates to a wafer edge trimming apparatus that includes a processing chamber defined by chamber housing. Within the processing chamber is a wafer chuck configured to hold onto a wafer structure. Further, a blade is arranged near an edge of the wafer chuck and configured to remove an edge potion of the wafer structure and to define a new sidewall of the wafer structure. A laser sensor apparatus is configured to direct a laser beam directed toward a top surface of the wafer chuck. The laser sensor apparatus is configured to measure a parameter of an analysis area of the wafer structure. Control circuitry is to the laser sensor apparatus and the blade. The control circuitry is configured to start a damage prevention process when the parameter deviates from a predetermined threshold value by at least a predetermined shift value.

Abstract: A battery module includes an insulating base, a pair of electrodes and multiple battery packs. Each electrode is installed to the insulating base and has a bridge portion and a wire connecting part exposed from the insulating base, and a pair of lugs is extended smoothly from each battery pack, and an end of at least a part of the lugs is attached to each bridge portion correspondingly. Therefore, the lug is not being twisted or deformed easily, and the battery module may have good conductive efficiency, long service life, and convenience of changing the battery pack.

Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.

Abstract: An organic optoelectronic device comprises a first electrode, an active layer and a second electrode. Active layer materials of the active layer comprise a block conjugated polymer materials which includes a structure of formula I: The polymer 1 is a p-type polymer with high energy gap, and the polymer 1 comprises a first electron donor and a first electron acceptor arranged alternately. The polymer 2 is a p-type polymer with low energy gap, and the polymer 2 comprises a second electron donor and a second electron acceptor arranged alternately. Wherein, o and p>0. The organic optoelectronic device of the present invention transfers carriers through the polymer 2 with low energy gap, and suppresses the recombination probability of carriers through the polymer 1 with high energy gap, thereby reducing the leakage current of the organic optoelectronic device.

Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.

Abstract: An overlay error measurement method includes disposing a lower-layer pattern over a substrate that includes disposing a first pattern having a first plurality of first sub-patterns extending in a first interval along a first direction and being arranged with a first pitch in a second direction crossing the first direction. The method includes disposing a second pattern having a second plurality of second sub-patterns extending in a second interval along the first direction and being arranged with a second pitch, smaller than the first pitch, in the second direction crossing the first direction. The second sub-patterns are disposed interleaved between the first sub-patterns. The method includes disposing an upper-layer pattern including a third pattern having the first pitch and at least partially overlapping with the lower-layer pattern over the lower-layer pattern and determining an overlay error between the lower-layer pattern and the upper-layer pattern.

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

Abstract: Some implementations described herein provide techniques and semiconductor devices in which a dielectric region is included in a nanostructure transistor. The dielectric region, which may correspond to an air gap, may be located between dielectric spacer layers located along a sidewall of a metal gate structure. Techniques to form the dielectric region may include using a temporary spacer layer between the dielectric spacer layers during manufacturing of the nanostructure transistor. The temporary spacer layer may include a silicon germanium material having a reaction mechanism that allows the temporary spacer layer to be selectively removed without causing damage to the dielectric spacer layers, the metal gate structure, or other portions of the nanostructure transistor.

Abstract: A structure includes a first conductive feature in a first dielectric layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer to physically contact the first conductive feature, wherein the second conductive feature includes a metal adhesion layer over and physically contacting the first conductive feature; a barrier layer extending along sidewalls of the second dielectric layer; and a conductive filling material extending over the metal adhesion layer and the barrier layer, wherein a portion of the conductive filling material extends between the barrier layer and the metal adhesion layer.

Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.

Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.