Patents by Inventor Minghsing Tsai
Minghsing Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11535950Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: GrantFiled: November 13, 2019Date of Patent: December 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 10985054Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: July 13, 2020Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20200343128Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 10714383Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: May 13, 2019Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20200080221Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: ApplicationFiled: November 13, 2019Publication date: March 12, 2020Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 10508356Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: GrantFiled: December 1, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Publication number: 20190326156Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: May 13, 2019Publication date: October 24, 2019Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 10290538Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: February 12, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20180174886Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: February 12, 2018Publication date: June 21, 2018Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 9892960Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: July 18, 2016Date of Patent: February 13, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20170081775Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: ApplicationFiled: December 1, 2016Publication date: March 23, 2017Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Patent number: 9518334Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.Type: GrantFiled: April 26, 2013Date of Patent: December 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
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Publication number: 20160329237Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 9401329Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); an upper low-k (LK) dielectric layer over the lower ESL; a first conductive feature in the upper LK dielectric layer, wherein the first conductive feature has a first metal line and a dummy via contiguous with the first metal line, the dummy via extending through the lower ESL; a first gap along an interface of the first conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the first conductive feature, and the first gap.Type: GrantFiled: March 12, 2013Date of Patent: July 26, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Patent number: 9214383Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.Type: GrantFiled: January 18, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Jiun Liu, Chien-An Chen, Ya-Lien Lee, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
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Patent number: 9142450Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a portion of a first low-k (LK) dielectric layer between the first metal line and the second metal line; and a second LK dielectric layer over the portion of the first LK dielectric layer. A top surface of the second LK dielectric layer is substantially coplanar with a top surface of the first metal line or the second metal line, and a thickness of the second LK dielectric layer is less than a thickness of the first metal line or a thickness of the second metal line.Type: GrantFiled: March 8, 2013Date of Patent: September 22, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeng-Shiou Chen, Chih-Yuan Ting, Jyu-Horng Shieh, Minghsing Tsai
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Publication number: 20150206724Abstract: The present disclosure is directed to a material layer deposition system. The material layer deposition system includes a wafer pedestal configured to support at least one wafer within a confinement shield structure and a target carrier structure positioned above the wafer pedestal at an opposite side of the confinement shield structure. The target carrier structure is configured to support a sputtering target. The material layer deposition system further includes a collimator disposed within the confinement shield structure between the wafer pedestal and the target carrier structure, an electrical power source coupled to the collimator to supply electrical power, and a control system configured to control the electrical power source coupled to the collimator.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Inventors: Shing-Chyang Pan, Ching-Hua Hsieh, Minghsing Tsai, Syun-Ming Jang
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Patent number: 9029260Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.Type: GrantFiled: June 16, 2011Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Chieh Lin, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
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Patent number: 8980745Abstract: A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.Type: GrantFiled: September 5, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh, Minghsing Tsai
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Patent number: 8975187Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.Type: GrantFiled: June 24, 2013Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai