Abstract: An electronic device may be provided with an antenna having a resonating element formed from a segment of peripheral conductive housing structures. A speaker may be aligned with first openings in the segment. A vent may be aligned with second openings in the segment. A connector may protrude through the segment. A trace combiner for the antenna may be patterned onto the speaker and may be coupled to the segment. Tuners for the antenna may be disposed on first and second flexible printed circuits that extend along opposing sides of the connector. The tuners may be controlled through the speaker. The second flexible printed circuit may extend along the vent. The vent may have a vent cowling with a cut-out region next to the tuner on the second flexible printed circuit.

Abstract: An electronic device may be provided with an antenna resonating element on a first substrate that is mounted to a second substrate. A signal conductor may be coupled to a feed terminal on the antenna resonating element. The signal conductor may include impedance matching structures for the antenna. The impedance matching structures may include an open transmission line stub, a grounded transmission line stub, and a phase shifting segment. The impedance matching structures may configure the antenna to exhibit a wide bandwidth in an ultra-wideband (UWB) frequency band. If desired, the signal conductor may have a phase-shifting segment configured to match a non-50 Ohm impedance of a radio-frequency front end coupled to the signal conductor.

Abstract: An electronic device may be provided with an antenna having a resonating element and a light source module mounted to a flexible printed circuit and a metal cowling. The module may emit light through a rear housing wall. The printed circuit may be interposed between the metal cowling and a conductive support plate in the rear housing wall. The printed circuit may include a ground trace coupled to the resonating element. A dimpled pad may couple the ground trace to the support plate. Compressive foam may be used to exert a force against the flexible printed circuit that presses the dimpled pad against the conductive support plate. The ground trace and the dimpled pad may form a return path to ground for the resonating element. The dimpled pad may occupy less height within the device than other structures such as metal springs.

Abstract: An electronic device may be provided with a housing and an antenna. The antenna may be on a first substrate mounted to a second substrate. The housing may include a dielectric cover, a conductive plate on the dielectric cover, and a mid-chassis. The second substrate may be mounted to the mid-chassis. The antenna may include a conductive patch extending from a segment of a conductive ring on the first substrate. The conductive plate may have an opening aligned with the conductive patch. The first substrate may be separated from the dielectric cover by an air gap. A conductive gasket may couple the conductive ring to the conductive plate and may laterally surround the air gap and the opening. The antenna may convey ultra-wideband (UWB) signals through the air gap, the opening, and the dielectric cover layer.

Abstract: An electronic device may be provided with an antenna having a resonating element formed from a segment of peripheral conductive housing structures. A speaker may be aligned with first openings in the segment. A vent may be aligned with second openings in the segment. A connector may protrude through the segment. A trace combiner for the antenna may be patterned onto the speaker and may be coupled to the segment. Tuners for the antenna may be disposed on first and second flexible printed circuits that extend along opposing sides of the connector. The tuners may be controlled through the speaker. The second flexible printed circuit may extend along the vent. The vent may have a vent cowling with a cut-out region next to the tuner on the second flexible printed circuit.

Abstract: This application provides a resource allocation method, a communication apparatus, and a computer-readable storage medium. An access point determines and sends a band indication and a resource unit allocation indication based on an RU/MRU allocated to a PPDU. The band indication indicates an index of a band of the RU/MRU, and an index range corresponding to the band indication in a first bandwidth is reused for an index range corresponding to the RU/MRU in a bandwidth of the PPDU. The resource unit allocation indication indicates an RU/MRU index of the RU/MRU on the band, and an index range corresponding to the resource unit allocation indication in the first bandwidth is also reused for an index range corresponding to the resource unit allocation indication in the bandwidth of the PPDU. The first bandwidth is greater than the bandwidth of the PPDU.

Abstract: An electronic device may be provided with peripheral conductive housing structures having first and second segments. A flexible printed circuit may have a first tail that extends along the first and second segments and a second tail that extends along the first segment. A conductive trace on the first tail may be coupled to an antenna feed terminal on the second segment. A conductive trace on the second tail may couple the conductive trace on the first tail to the first segment. A tuner and filters may be disposed on the flexible printed circuit and may be coupled to the conductive traces. The conductive trace on the second tail may have a tapered width. An antenna in the device may have a resonating element that includes both the first and second segments, thereby allowing the antenna to exhibit a wide bandwidth from 1.1-5 GHz.

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Abstract: A pixel array includes a plurality of sub-pixels, which include first to third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form first pixel rows. The first and third sub-pixels, which are in a same column, in the first pixel rows are alternately arranged, and the second sub-pixels are arranged side by side along the row direction and form second pixel rows. Lines sequentially connecting centers of two of the first sub-pixels and two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. A straight line in the row direction or in a column direction, which passes through a center of each sub-pixel of at least one of the plurality of sub-pixels, divides the sub-pixel into two parts having areas different from each other.

Abstract: Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Abstract: Display substrate, display device, high-precision metal mask are provided. Display substrate includes: first, second, and third sub-pixels; in first direction, first and third sub-pixels are alternately arranged to form first sub-pixel rows, second sub-pixels form second sub-pixel rows; in second direction, first and second sub-pixel rows are alternately arranged; two first and two third sub-pixels in two adjacent rows and two adjacent columns form 2*2 array; in the array, two first sub-pixels are in different rows and in different columns, so are the two third sub-pixels, connection lines of centers of two first and two third sub-pixels form virtual quadrilateral, second sub-pixel is within virtual quadrilateral; for multiple distances from centers of two first and two third sub-pixels corresponding to same virtual quadrilateral to center of second sub-pixel, at least two distances are different. Brightness centers of virtual pixels have more uniform distribution.

Abstract: A pixel circuit is disposed in the display substrate, the display substrate includes a display stage and a non-display stage, the pixel circuit is configured to drive the light emitting element to emit light in the display stage, and includes a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit, a light emitting control sub-circuit and a driving sub-circuit; the third control sub-circuit is electrically connected with a third reset signal terminal, a control signal terminal and a third node respectively, and is configured to provide a first signal to the third node in the display stage and a second signal to the third node or acquire a signal of the third node in the non-display stage under control of the third reset signal terminal.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate, sub-pixels, a pixel defining layer having openings, spacers on the pixel defining layer. A shape of at least one of the openings is a polygon with at least one vertex angle cut off, and a corner portion of the opening includes a first corner portion formed by cutting off one vertex angle included between two sides of the polygon from the polygon. At least one of the spacers is arranged at an interval between the first corner portion and the opening adjacent to the first corner portion, and a connecting line between a geometric center of the opening where the first corner portion is located and a geometric center of the opening adjacent to the first corner portion passes through the first corner portion and the spacer.

Abstract: An authorized access list generation method including: at least one network service providing device registering for an authorized access list notification service with a server, the authorized access list including at least one authorization related record of at least one legitimate user device; the legitimate user device outputting a user ID to the server to log into the server, and directly sending an access request to a target network service provider after logging into the server, and continuing to provide an IP address being used and a device ID to the server to update a corresponding authorization related record; and the target network service providing device comparing the IP address, stored in each authorization related record of the authorized access list, with the IP address of a user device issuing an access request, and rejecting the access request if no matched result is found.

Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

Abstract: There is provided a pixel array including a plurality of sub-pixels, which include first sub-pixels, second sub-pixels, and third sub-pixels. The first and third sub-pixels are alternately arranged along a row direction and form a plurality of first pixel rows, the first and third sub-pixels, which are in a same column, in the plurality of first pixel rows are alternately arranged, and the second sub-pixels are arranged along the row direction and form second pixel rows. Lines sequentially connecting centers of any two of the first sub-pixels and any two of the third sub-pixels, which are arranged in an array, together form a first virtual quadrilateral, and one of the second sub-pixels is in each first virtual quadrilateral. At least one interior angle of the first virtual quadrilateral is not 90°. At least one of the first, second and third sub-pixels has a corner circularly or rectilinearly chamfered.

Abstract: Techniques are described herein for an integrated in-front database cache (“IIDC”) providing an in-memory, consistent, and automatically managed cache for primary database data. An IIDC comprises a database server instance that (a) caches data blocks from a source database managed by a second database server instance, and (b) performs recovery on the cached data using redo records for the database data. The IIDC instance implements relational algebra and is configured to run any complexity of query over the cached database data. Any cache miss results in the IIDC instance fetching the needed block(s) from a second database server instance managing the source database that provides the IIDC instance with the latest version of the requested data block(s) that is available to the second instance. Because redo records are used to continuously update the data blocks in an IIDC cache, the IIDC guarantees consistency of query results.