Patents by Inventor Ming-Hua Tsai
Ming-Hua Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996227Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.Type: GrantFiled: December 13, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
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Publication number: 20240153896Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 11969448Abstract: A probiotic composition for improving an effect of a chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is disclosed in the present disclosure. The probiotic composition comprises an effective amount of Lactobacillus paracasei GMNL-133, an effective amount of Lactobacillus reuteri GMNL-89, and a pharmaceutically acceptable carrier, wherein the Lactobacillus paracasei GMNL-133 was deposited in the China Center for Type Culture Collection on Sep. 26, 2011 under an accession number CCTCC NO. M 2011331, and the Lactobacillus reuteri GMNL-89 was deposited in the China Center for Type Culture Collection on Nov. 19, 2007 under an accession number CCTCC NO. M 207154. A method for improving the effect of the chemotherapeutic drug of Gemcitabine on inhibiting pancreatic cancer is further disclosed in the present disclosure.Type: GrantFiled: May 12, 2021Date of Patent: April 30, 2024Assignee: GENMONT BIOTECH INC.Inventors: Wan-Hua Tsai, I-ling Hsu, Shan-ju Hsu, Wen-ling Yeh, Ming-shiou Jan, Wee-wei Chieng, Li-jin Hsu, Ying-chun Lai
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Publication number: 20240134149Abstract: An imaging lens module with auto focus function includes an imaging lens assembly, an electromagnetic driving component assembly and a lens carrier. The imaging lens assembly has an optical axis. The electromagnetic driving component assembly drives the imaging lens assembly to move in a direction parallel to the optical axis by a Lorentz force. The imaging lens assembly is mounted to the lens carrier such that the imaging lens assembly can be wholly driven by the Lorentz force. The lens carrier includes an object-side part, a mounting structure and a plurality of plate portions. The object-side part includes a tip-end minimal aperture configured for light to travel through; and a tapered surface which surrounds an area tapered off from image side to object side. The mounting structure and the plate portions are configured for at least a part of the electromagnetic driving component assembly to be mounted thereto.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Applicant: LARGAN DIGITAL CO.,LTD.Inventors: Chun-Hua TSAI, Ming-Ta CHOU, Ming-Shun CHANG
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Patent number: 11964428Abstract: The present invention provides a bottom plate of a resin tank for three-dimensional printing, which is manufactured through the following steps: substrate surface roughening step: treating the upper surface of a transparent substrate by using a plasma, or disposing a composite film on the upper surface of the transparent substrate to form a non-smooth surface structure having pores; substrate surface modification step: sequentially performing an activation treatment and a fluorination treatment on the upper surface of the transparent substrate; and stabilizer filling step: applying a stabilizer to the upper surface of the transparent substrate to fill the stabilizer penetrates into the pores on the upper surface of the transparent substrate. The low surface energy film reduces the adhesion of the hardened photosensitive material, and the stabilizer maintains the structure of the low surface energy film, so that the resin tank bottom plate has both oleophobic and hydrophobic properties.Type: GrantFiled: March 10, 2022Date of Patent: April 23, 2024Assignee: National Taiwan University of Science and TechnologyInventors: Jeng-Ywan Jeng, Ming-Hua Ho, Ping-Hsun Tsai
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Patent number: 11923455Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.Type: GrantFiled: June 10, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
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Publication number: 20240038684Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.Type: ApplicationFiled: August 16, 2022Publication date: February 1, 2024Applicant: United Microelectronics Corp.Inventors: Ming-Hua Tsai, Hao Ping Yan, Chin-Chia Kuo, Wei Hsuan Chang
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Publication number: 20230335609Abstract: The invention provides a transistor structure and a manufacturing method thereof. The transistor structure includes a substrate, a first gate, a second gate, a first gate dielectric layer, and a second gate dielectric layer. The first gate and the second gate are located on the substrate. The first gate dielectric layer is located between the first gate and the substrate. The first gate dielectric layer has a single thickness. The second gate dielectric layer is located between the second gate and the substrate. The second gate dielectric layer has a plurality of thicknesses. A maximum thickness of the first gate dielectric layer is the same as a maximum thickness of the second gate dielectric layer. The transistor structure may reduce process complexity.Type: ApplicationFiled: May 3, 2022Publication date: October 19, 2023Applicant: United Microelectronics Corp.Inventors: Ming-Hua Tsai, Wei Hsuan Chang, Chin-Chia Kuo
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Publication number: 20230261092Abstract: A fabricating method of a middle voltage transistor includes providing a substrate. A gate predetermined region is defined on the substrate. Next, a mask layer is formed to cover only part of the gate predetermined region. Then, a first ion implantation process is performed to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions. After removing the mask layer, a gate is formed to overlap the entirety gate predetermined region. Subsequently, two second lightly doping regions respectively formed within one of the first lightly doping regions. Next, two source/drain doping regions are respectively formed within one of the second lightly doping regions. Finally, two silicide layers are formed to respectively cover one of the source/drain doping regions.Type: ApplicationFiled: March 15, 2022Publication date: August 17, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Hao-Ping Yan, Ming-Hua Tsai, Chin-Chia Kuo
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Publication number: 20230207647Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.Type: ApplicationFiled: March 1, 2023Publication date: June 29, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
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Patent number: 11626500Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.Type: GrantFiled: July 8, 2021Date of Patent: April 11, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
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Publication number: 20230105690Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.Type: ApplicationFiled: December 8, 2022Publication date: April 6, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
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Patent number: 11569380Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.Type: GrantFiled: July 2, 2021Date of Patent: January 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
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Publication number: 20230006062Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.Type: ApplicationFiled: July 2, 2021Publication date: January 5, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
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Patent number: 11545447Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.Type: GrantFiled: August 4, 2021Date of Patent: January 3, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
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Publication number: 20220376071Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.Type: ApplicationFiled: July 8, 2021Publication date: November 24, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ming-Hua Tsai, Jung Han, Ming-Chi Li, Chih-Mou Lin, Yu-Hsiang Hung, Yu-Hsiang Lin, Tzu-Lang Shih
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Publication number: 20210366843Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
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Patent number: 11114390Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.Type: GrantFiled: January 9, 2020Date of Patent: September 7, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
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Publication number: 20210217705Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.Type: ApplicationFiled: January 9, 2020Publication date: July 15, 2021Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo