Abstract: A frame layout and method for determining the overlay accuracy of a first chip image relative to a second chip image when the first and second chip images are used to form a single chip. One embodiment employs a vernier scale in two orthoginal directions included in the scribeline of both the first chip image and the second chip image. Another embodiment employs a box in box pattern included in the scribeline of both the first chip image and the second chip image. A layer of photoresist on an integrated circuit wafer is exposed with the first and second chip image and the associated monitor images. When the photoresist is developed the overlay accuracy of the first chip image relative to the second chip image can be determined directly from the monitor images in the photoresist.

Abstract: Single spot laser focusing systems are widely used by photolithographic stepping systems. The stage is moved until a spot, located in the immediate area in which the image is to be projected, achieves minimum size. This system is sensitive to the local topography within the area of the image and this can lead to less than optimum results. The present invention overcomes this problem by a process in which the spot is always directed to fall within an alignment mark field (as opposed to within the integrated circuit field). Several ways for accomplishing this are described.