Abstract: A system and method of decomposing a single photoresist mask pattern to three photoresist mask patterns. The system and method assign nodes to polygon features on the single photoresist mask pattern, designate nodes as being adjacent nodes for those nodes that are less than a predetermined distance apart, iteratively remove nodes having 2 or less adjacent nodes until no nodes having 2 or less adjacent nodes remain, identify one or more internal nodes, map photoresist mask pattern designations (colors) to the internal nodes, and replace and map a color to each of the nodes removed by the temporarily removing nodes, such that each node does not have an adjacent node of the same color.

Abstract: A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.

Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

Abstract: A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines.

Abstract: A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing.

Abstract: A method includes determining one or more potential merges corresponding to a color set Ai and a color set Aj of N color sets, represented by A1 to AN, used in coloring polygons of a layout of an integrated circuit. N is a positive integer, i and j are integers from 1 to N, and i?j. One or more potential cuts corresponding to the color set Ai and the second color set Aj are determined. An index Aij is determined according to the one or more potential merges and the one or more potential cuts. A plurality of parameters F related to the index Aij is obtained based on various values of indices fi and fj. A parameter F is selected among the plurality of parameters F based on a definition of the index Aij.

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern.

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout.

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract: Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio.

Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.