Patents by Inventor Ming-Hung Wang
Ming-Hung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240144966Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a first lower shield, a first sensor disposed over the first lower shield, a first upper shield disposed over the first sensor, a read separation gap (RSG) disposed on the first upper shield, a second lower shield disposed over the RSG, a second sensor disposed over the second lower shield, and a second upper shield disposed over the second sensor. In some embodiments, the second lower shield comprises a CoFeHf layer. In another embodiment, the second lower shield is a synthetic antiferromagnetic multilayer comprising a first shield layer, a second shield layer, and a CoFe/Ru/CoFe anti-ferromagnetic coupling layer or a Ru layer disposed therebetween, the first and second shield layers comprising NiFe and CoFe. In yet another embodiment, the second lower shield comprises layers of Ru, IrMn, and NiFe.Type: ApplicationFiled: July 26, 2023Publication date: May 2, 2024Applicant: Western Digital Technologies, Inc.Inventors: Ming MAO, Chen-Jung CHIEN, Goncalo Marcos BAIÃO DE ALBUQUERQUE, Chih-Ching HU, Yung-Hung WANG, Ming JIANG
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Publication number: 20240145461Abstract: A modulation device includes a substrate, an electrostatic discharge protection element, an electronic element, and a driving element. The substrate has an active region. The electrostatic discharge protection element is arranged around the active region. The electronic element is disposed in the active region. The driving element is electrically connected to the electronic element.Type: ApplicationFiled: October 4, 2023Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Ker-Yih Kao, Tong-Jung Wang, Wen-Chieh Lin, Ming-Chun Tseng, Yi-Hung Lin
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Patent number: 11955507Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
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Patent number: 11948936Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a fin disposed in a first region of the semiconductor device, channel members disposed in a second region of the semiconductor device and stacked in a vertical direction, first and second metal gates disposed on a top surface of the fin, a third metal gate wrapping around each of the channel members, a first implant region in the fin with a first conductivity type, and a second implant region in the fin with a second conductivity opposite the first conductivity type. The fin includes first and second type epitaxial layers alternatingly disposed in the vertical direction. The first and second type epitaxial layers have different material compositions. The first type epitaxial layers and the channel members have the same material composition.Type: GrantFiled: April 24, 2023Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Wang, Chih Chieh Yeh, Zi-Ang Su, Chia-Ju Chou, Ming-Shuan Li
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Patent number: 11931456Abstract: A pharmaceutical composition containing a mixed polymeric micelle and a drug enclosed in the micelle, in which the mixed polymeric micelle, 1 to 1000 nm in size, includes an amphiphilic block copolymer and a lipopolymer. Also disclosed are preparation of the pharmaceutical composition and use thereof for treating cancer.Type: GrantFiled: November 16, 2022Date of Patent: March 19, 2024Assignee: MegaPro Biomedical Co. Ltd.Inventors: Ming-Cheng Wei, Yuan-Hung Hsu, Wen-Yuan Hsieh, Chia-Wen Huang, Chih-Lung Chen, Jhih-Yun Jian, Shian-Jy Wang
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Publication number: 20240087823Abstract: A keyboard and a key structure capable of displaying instant image thereof are provided. The key structure includes a display unit, a circuit membrane, an elastic member, a key seat, a first supporting frame, a second supporting frame, and a translucent keycap. The first supporting frame has two first arms and two axle portions. The ends of the first arms are slidably disposed on an accommodation portion of the key seat. The second supporting frame has two second arms and two linking holes. The ends of the second arms are pivotally connected to the accommodation portion. The linking hole is elongated-shaped. When the translucent keycap is not pressed, the axle portion abuts against one hole-end of the linking hole. When the translucent keycap is pressed, the axle portion abuts against another one hole-end of the linking hole.Type: ApplicationFiled: September 8, 2022Publication date: March 14, 2024Inventors: MING-HUNG WANG, CHIA-HSIN TSAI
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Publication number: 20240075449Abstract: The application relates to a polymerization vessel and a method for manufacturing the same. An interior surface of the polymerization vessel has a specific structure, so that the polymerization vessel has better heat transfer efficiency. Closed cooling channels are constructed from the specific structure, and therefore cooling fluid flows in the closed cooling channels. Furthermore, there won't be any by-pass defects in the cooling channels of the polymerization vessel, thereby improving cooling efficiency of the cooling fluid.Type: ApplicationFiled: March 30, 2023Publication date: March 7, 2024Inventors: Ming-Hung CHENG, Fuh-Yih SHIH, Shih-Ming YEH, Wen-Yi WANG
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Publication number: 20240071413Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Applicant: Western Digital Technologies, Inc.Inventors: Ming MAO, Yung-Hung WANG, Chih-Ching HU, Chen-Jung CHIEN, Carlos CORONA, Hongping YUAN, Ming JIANG, Goncalo Marcos BAIÃO DE ALBUQUERQUE
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Patent number: 11916131Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.Type: GrantFiled: November 4, 2020Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
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Patent number: 11755685Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.Type: GrantFiled: September 15, 2021Date of Patent: September 12, 2023Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Ming-Hung Wang, Cheng-En Shieh
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Patent number: 11721390Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: GrantFiled: January 5, 2022Date of Patent: August 8, 2023Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Patent number: 11437087Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.Type: GrantFiled: July 1, 2020Date of Patent: September 6, 2022Assignee: Piecemakers Technology, Inc.Inventors: Ming-Hung Wang, Chun-Peng Wu
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Publication number: 20220130450Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: ApplicationFiled: January 5, 2022Publication date: April 28, 2022Applicant: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Publication number: 20220100816Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.Type: ApplicationFiled: September 15, 2021Publication date: March 31, 2022Applicant: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Ming-Hung Wang, Cheng-En Shieh
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Patent number: 11250904Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.Type: GrantFiled: September 30, 2020Date of Patent: February 15, 2022Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
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Patent number: 11183231Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.Type: GrantFiled: June 17, 2020Date of Patent: November 23, 2021Assignee: Piecemakers Technology, Inc.Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
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Publication number: 20210158853Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.Type: ApplicationFiled: July 1, 2020Publication date: May 27, 2021Inventors: Ming-Hung Wang, Chun-Peng Wu
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Publication number: 20210158856Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.Type: ApplicationFiled: June 17, 2020Publication date: May 27, 2021Inventors: Gyh-Bin Wang, Ming-Hung Wang, Tah-Kang Joseph Ting
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Patent number: 9997224Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.Type: GrantFiled: January 24, 2017Date of Patent: June 12, 2018Assignee: Piecemakers Technology, Inc.Inventors: Ming-Hung Wang, Gyh-Bin Wang, Tah-Kang Joseph Ting
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Publication number: 20180068700Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.Type: ApplicationFiled: January 24, 2017Publication date: March 8, 2018Inventors: Ming-Hung Wang, Gyh-Bin Wang, Tah-Kang Joseph Ting