Patents by Inventor Ming-I Chen
Ming-I Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162602Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.Type: ApplicationFiled: January 2, 2024Publication date: May 16, 2024Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN
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Publication number: 20240145421Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
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Publication number: 20240126327Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
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Publication number: 20240099695Abstract: A capacitive ultrasonic transducer device includes a substrate, a first capacitive structure, a second capacitive structure, a first film structure and a second film structure. The first capacitive structure is disposed on the substrate, and includes a first electrode and a second electrode. A first gap and a dielectric layer are located between the first electrode and the second electrode. The second capacitive structure is disposed on the substrate, and includes a third electrode and a fourth electrode. A second gap is located between the third electrode and the fourth electrode. The first film structure is configured to seal the first gap. The second film structure is connected to the third electrode and the fourth electrode, and configured to seal the second gap. A first width between the first electrode and the second electrode is different from a second width of the second gap.Type: ApplicationFiled: December 18, 2022Publication date: March 28, 2024Inventors: Sheng-Shian LI, Hung-Yu CHEN, Ming-Huang LI, Po-I SHIH
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Publication number: 20240088156Abstract: A semiconductor device includes at least one fin, a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed on the at least one fin. The second dielectric layer between the at least one fin and the first dielectric layer. A thickness of the first dielectric layer on a sidewall of the at least one fin is less than a thickness of the second dielectric layer on the sidewall of the at least one fin.Type: ApplicationFiled: November 23, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-I Lin, Chun-Heng Chen, Ming-Ho Lin, Chi-On Chui
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Patent number: 8426922Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.Type: GrantFiled: October 15, 2010Date of Patent: April 23, 2013Assignee: United Microelectronics Corp.Inventors: Fang-Mei Chao, Ming-I Chen, Ying-Ko Chin, Yi-Chiao Wang
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Patent number: 8318559Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.Type: GrantFiled: October 19, 2010Date of Patent: November 27, 2012Assignee: United Microelectronics Corp.Inventors: Ming-I Chen, Fang-Mei Chao
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Publication number: 20120091536Abstract: A CMOS structure includes a PMOS portion and an NMOS portion isolated from each other via a P-well region disposed next to the PMOS portion and an N-well region disposed between the P-well region and the NMOS portion, an insulation layer overlying at least the N-well region, and a pad structure disposed over the N-well region. The pad structure further includes: a pad body disposed on the insulation layer; and at least one contact plug penetrating through the insulation layer, having one end coupled to the pad body and the other end coupled to a contact zone in the N-well region; wherein the contact zone is interfaced with the N-well region with P-type dopants.Type: ApplicationFiled: October 15, 2010Publication date: April 19, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Fang-Mei CHAO, Ming-I Chen, Ying-Ko Chin, Yi-Chiao Wang
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Publication number: 20110033993Abstract: The Complementary Metal-Oxide Semiconductor (CMOS) transistor of the present invention includes deep halo doped regions in the substrate. The fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.Type: ApplicationFiled: October 19, 2010Publication date: February 10, 2011Inventors: Ming-I Chen, Fang-Mei Chao
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Patent number: 7843012Abstract: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.Type: GrantFiled: January 31, 2007Date of Patent: November 30, 2010Assignee: United Microelectronics Corp.Inventors: Ming-I Chen, Fang-Mei Chao
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Patent number: 7791137Abstract: A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: GrantFiled: February 1, 2007Date of Patent: September 7, 2010Assignee: United Microelectronics Corp.Inventors: Chih-Hua Lee, Ming-I Chen
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Patent number: 7462532Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: GrantFiled: October 11, 2007Date of Patent: December 9, 2008Assignee: United Microelectronics Corp.Inventors: Chih-Hua Lee, Ming-I Chen
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Publication number: 20080179686Abstract: The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains or the source/drain doped regions, and therefore no extra mask is required.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Inventors: Ming-I Chen, Fang-Mei Chao
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Patent number: 7375408Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: GrantFiled: October 11, 2005Date of Patent: May 20, 2008Assignee: United Microelectronics Corp.Inventors: Chih-Hua Lee, Ming-I Chen
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Publication number: 20080032445Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: ApplicationFiled: October 11, 2007Publication date: February 7, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Hua Lee, Ming-I Chen
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Publication number: 20070128788Abstract: A high voltage metal oxide semiconductor device including a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: ApplicationFiled: February 1, 2007Publication date: June 7, 2007Applicant: United Microelectronics Corp.Inventors: Chih-Hua Lee, Ming-I Chen
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Publication number: 20070080398Abstract: A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Inventors: Chih-Hua Lee, Ming-I Chen
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Patent number: 6583484Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.Type: GrantFiled: March 1, 2001Date of Patent: June 24, 2003Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Ming-I Chen
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Publication number: 20010055849Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.Type: ApplicationFiled: March 1, 2001Publication date: December 27, 2001Inventors: Jui-Hsiang Pan, Ming-I Chen
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Patent number: 6329233Abstract: A method for manufacturing a photodiode CMOS image sensor. A first well and a second well are formed in a first type substrate. An isolation layer is formed over the first well and the second well. At the same time, an isolation layer is formed over another region to pattern out an active region for forming the photodiode. A protective ring layer is formed over the peripheral area of the photodiode active region. A first gate structure and a second gate structure are formed above the first well and the second well respectively. A first type source/drain region and a second type source/drain region are formed in the first well and the second well respectively. Concurrently, a second type heavily doped layer is formed in the first type substrate inside the area enclosed by the protective ring layer. A high-energy ion implantation is carried out to form a second type lightly doped layer in the first type substrate just outside the second type heavily doped layer.Type: GrantFiled: June 23, 2000Date of Patent: December 11, 2001Assignee: United Microelectronics Corp.Inventors: Jui-Hsiang Pan, Ming-I Chen