Patents by Inventor Ming-Jang Lin
Ming-Jang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8138047Abstract: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on the N+ substrate. The silicon dioxide layer is disposed between the N-type layer and the P-type layer. The P+ layer is disposed on the P-type layer and the N-type layer.Type: GrantFiled: April 7, 2009Date of Patent: March 20, 2012Assignee: inergy Technology Inc.Inventor: Ming-Jang Lin
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Publication number: 20090250727Abstract: In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N+ substrate, a N-type layer, a silicon dioxide layer and a P+ layer. The N+ substrate is disposed under the P-type layer. The N-type layer is disposed on the N+ substrate. The silicon dioxide layer is disposed between the N-type layer and the P-type layer. The P+ layer is disposed on the P-type layer and the N-type layer.Type: ApplicationFiled: April 7, 2009Publication date: October 8, 2009Applicant: INERGY TECHNOLOGY INC.Inventor: MING-JANG LIN
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Publication number: 20090114983Abstract: A power transistor capable of decreasing capacitance between a gate and a drain includes a backside mental layer, a substrate formed on the backside mental layer, a semiconductor layer formed on the substrate, and a frontside mental layer formed on the semiconductor layer. The semiconductor layer comprises a first trench structure comprising a gate oxide layer, a second trench structure comprising a p-well junction formed around a second trench, a p-body region formed outside the first trench structure and the second trench structure, a first n+ source region formed on the p-body region and beside a sidewall of the first trench structure, a second n+ source region formed on the p-body region and between another sidewall of the first trench structure and the second trench structure, and a dielectric layer formed on the first trench structure, the first n+ source region, and the second n+ source region.Type: ApplicationFiled: June 20, 2008Publication date: May 7, 2009Inventors: Wei-Chieh Lin, Jen-Hao Yeh, Ming-Jang Lin
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Publication number: 20090117700Abstract: A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal.Type: ApplicationFiled: June 9, 2008Publication date: May 7, 2009Inventors: Wei-Chieh Lin, Jen-Hao Yeh, Ming-Jang Lin
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Publication number: 20090061584Abstract: The present invention provides a semiconductor process for a trench power MOSFET. The semiconductor process includes providing a substrate, forming an EPI wafer on the surface, performing trench dry etching, performing HTP hard mask oxide deposition and channel self- align implant, performing boron (B) implant and completing the P-body region through a thermal process, performing arsenic (As) implant and completing the n+ source region through a thermal process, and depositing BPSG ILD, front side metal Al, and backside metal Ti/Ni/Ag.Type: ApplicationFiled: February 12, 2008Publication date: March 5, 2009Inventors: Wei-Chieh Lin, Jen-Hao Yeh, Ming-Jang Lin, Hsin-Yen Chiu
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Publication number: 20070181948Abstract: The junction breakdown voltage of an ESD protection device is adjusted by altering the distance between two diffusion regions of opposite conductivity types.Type: ApplicationFiled: August 3, 2006Publication date: August 9, 2007Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Wei-Jye Lin
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Publication number: 20070114601Abstract: A gate contact structure for a power device comprises a substrate having a trench, a gate conductor in the trench and striding over a side of the trench, a first insulator between the gate conductor and the trench, a second insulator covering the gate conductor, a contact window in the second insulator above the trench and striding the side of the trench to expose a surface of the underlying gate conductor, and a gate metal electrically contacting the gate conductor through the contact window.Type: ApplicationFiled: September 15, 2006Publication date: May 24, 2007Inventors: Wei-Jye Lin, Ming-Jang Lin, Chorng-Wei Liaw
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Patent number: 7105410Abstract: A contact process for a semiconductor device containing a base region of a first conductivity type formed on a semiconductor substrate comprises formation of a first shallow layer of the first conductivity type on the base region, deposition of an insulator on the first shallow layer, etching the insulator and first shallow layer to form a contact hole, thermally driving the first shallow layer more deeply into said base region, formation of a second shallow layer of a second conductivity type on the base region at the bottom of the contact hole, filling a metal in the contact hole to contact the sidewall of the first shallow layer and the second shallow layer.Type: GrantFiled: April 9, 2004Date of Patent: September 12, 2006Assignee: Analog and Power Electronics Corp.Inventors: Wei-Jye Lin, Ming-Jang Lin, Chorng-Wei Liaw
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Publication number: 20050224869Abstract: A contact process for a semiconductor device containing a base region of a first conductivity type formed on a semiconductor substrate comprises formation of a first shallow layer of the first conductivity type on the base region, deposition of an insulator on the first shallow layer, etching the insulator and first shallow layer to form a contact hole, thermally driving the first shallow layer more deeply into said base region, formation of a second shallow layer of a second conductivity type on the base region at the bottom of the contact hole, filling a metal in the contact hole to contact the sidewall of the first shallow layer and the second shallow layer.Type: ApplicationFiled: April 9, 2004Publication date: October 13, 2005Inventors: Wei-Jye Lin, Ming-Jang Lin, Chorng-Wei Liaw
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Patent number: 6888203Abstract: A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.Type: GrantFiled: February 7, 2003Date of Patent: May 3, 2005Assignee: Analog and Power Electrics Corp.Inventors: Chorng-Wei Liaw, Hau-Luen Tien, Wei-Jye Lin, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu
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Publication number: 20040195689Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.Type: ApplicationFiled: April 27, 2004Publication date: October 7, 2004Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Wei-Jye Lin
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Patent number: 6800509Abstract: A process for a trench power MOSFET comprises forming a trench on a semiconductor substrate and an oxide and nitride in the trench, etching the oxide and nitride to remain a part of them at the bottom of the trench, and subsequent procedure for the other structure of the trench power MOSFET. Due to the thick insulator formed at the bottom of the trench, the trench power MOSFET is improved by increased voltage endurance and reduced parasitic capacitance, and thereby the cell density is increased.Type: GrantFiled: June 24, 2003Date of Patent: October 5, 2004Assignee: Anpec Electronics CorporationInventors: Ming-Jang Lin, Chorng-Wei Liaw, Wei-Jye Lin
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Publication number: 20030141555Abstract: A butting contact structure using a silicide to connect a contact region and a conductor and a method to manufacture the same are disclosed. The method comprises the steps of: forming a first area having a first conduction type and a second area having a second conduction type which is adjacent to the first area; forming a silicide to be in contact with the first and second areas; and depositing an insulating layer covering the first portion of the silicide; etching a contact window in the insulating layer for exposing a surface of the silicide; and forming a conductor filling in the contact window. The difficulty from the reduction of the contact window is overcome without altering the manufacturing process and the layer of masks. Moreover, the density and performance of the semiconductor element is improved.Type: ApplicationFiled: January 3, 2003Publication date: July 31, 2003Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Wei-Jye Lin
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Publication number: 20030117825Abstract: A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.Type: ApplicationFiled: February 7, 2003Publication date: June 26, 2003Inventors: Chorng-Wei Liaw, Hau-Luen Tien, Wei-Jye Lin, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu
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Patent number: 6423618Abstract: A method for manufacturing a trench gate structure of a power metal-oxide-semiconductor field-effect transistor. A substrate is provided, which substrate has a epitaxial layer thereon, a base region formed in the epitaxial layer, a source region formed in a portion of the base region, a first dielectric layer on the base region and the source region, a second dielectric layer on the first dielectric layer and a trench penetrating through the second and the first dielectric layers, the source region and the base region and into the epitaxial layer. A third dielectric layer is formed on the bottom of the trench. A conformal gate oxide layer is formed in the trench. A conformal polysilicon layer is formed on the second dielectric layer and in the trench. A fourth dielectric layer is formed on the polysilicon layer to fill the trench.Type: GrantFiled: December 15, 1999Date of Patent: July 23, 2002Assignee: Analog and Power Electronics Corp.Inventors: Ming-Jang Lin, Chorng-Wei Liaw, Tian-Fure Shiue, Ching-Hsiang Hsu, Huang-Chung Cheng
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Publication number: 20020053695Abstract: A split buried layer for high voltage lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor formed on a semiconductor substrate is disclosed to increase the breakdown voltage of the LDMOS. The LDMOS comprises a drain, a source, a gate channel between the drain and source, a gate to control the gate channel, a drift region between the drain and gate channel, and the buried layer between the drift region and the substrate. The improvement is that at least one field trap is formed in the buried layer under the drift region. A method of forming the split buried layer comprises formation of a lightly doped region or a doping discontinuity at a position corresponding to the field trap, and then driving the dopant to form a doping concentration profile laterally-split at the field trap. In other embodiment methods, the split buried layer is formed by a recess in thickness, or a lighter or deeper profile in concentration at the field trap.Type: ApplicationFiled: July 30, 2001Publication date: May 9, 2002Inventors: Chorng-Wei Liaw, Chin-Horng Chang, Wei-Jye Lin, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu
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Publication number: 20010046147Abstract: A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.Type: ApplicationFiled: June 15, 2001Publication date: November 29, 2001Inventors: Chorng-Wei Liaw, Hau-Luen Tien, Wei-Jye Lin, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu
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Patent number: 6259618Abstract: A power chip set for a switching mode power supply includes a high voltage chip and a control unit chip. The high voltage chip contains a switching power metal-oxide-semiconductor (MOS) transistor being turned on/off under control of an output signal from the control unit, and a junction field effect transistor (JFET) coupled between a drain of the switching power MOS transistor and a power terminal of the control unit to serve as a start up element for driving the control unit during initiation, in which the JFET has a negative threshold voltage and the absolute value thereof is equal to the voltage for driving the control unit. The JFET structure in the high voltage chip further includes a Zener diode for over voltage protection of the control unit. The high voltage chip further contains a current-sense power MOS transistor coupled with the drain of the switching power MOS transistor for detecting a drain current of the switching power MOS transistor. The chip set can be packaged into a power module.Type: GrantFiled: May 3, 2000Date of Patent: July 10, 2001Assignee: Analog and Power Electronics Corp.Inventors: Chorng-Wei Liaw, Hau-Luen Tien, Wei-Jye Lin, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu
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Patent number: 6137122Abstract: A latch-up controllable insulated gate bipolar transistor is formed with a thyristor structure, which has a first region of a first conductivity type, a second region of a second conductivity type formed on the first region, a third region of the first conductivity type formed on the second region, and a fourth region of the second conductivity type contacting the third region and forming a P-N junction therewith. The first and third regions contact a first and second electrode regions respectively. A first field effect transistor means for controlling conduction between the fourth region and the second region in response to an actuation bias; and a second field effect transistor means between the fourth region and the second electrode region for turning the thyristor off in response to a cutoff bias.Type: GrantFiled: December 2, 1999Date of Patent: October 24, 2000Assignee: Analog and Power Electronics Corp.Inventors: Chorng-Wei Liaw, Ming-Jang Lin, Tian-Fure Shiue, Huang-Chung Cheng, Ching-Hsiang Hsu, Wei-Jye Lin, Hau-Luen Tien