Patents by Inventor Ming Jiang

Ming Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153533
    Abstract: The present disclosure generally relates to a dual free layer (DFL) two dimensional magnetic recording (TDMR) read head, and a method of forming thereof. The read head comprises a lower sensor, middle shields disposed on the lower sensor, and an upper sensor disposed on the middle shields. After the lower reader is formed, a dielectric layer is deposited around an outer perimeter of the lower shield. Portions of the dielectric layer are ion milled such that the remaining portions form a substantially flat layer. Another embodiment includes a deposition of a TaOx layer on the dielectric layer, where x is a numeral. Portions of the dielectric layer and the TaOx layer are then ion milled such that the remaining portions of the TaOx layer and the dielectric layer collectively form a substantially planar layer. The middle shields are formed over the lower reader and are substantially planar.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 9, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Hongquan JIANG, Guanxiong LI, Ming MAO
  • Patent number: 11977947
    Abstract: The present invention provides an electronic shelf label communication system, method and apparatus.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 7, 2024
    Assignee: Hanshow Technology Co., Ltd.
    Inventors: Shiguo Hou, Liangyan Li, Yunliang Feng, Bo Gao, Jun Chen, Qi Jiang, Ming Shen
  • Publication number: 20240144966
    Abstract: The present disclosure generally relates to a dual free layer two dimensional magnetic recording read head. The read head comprises a first lower shield, a first sensor disposed over the first lower shield, a first upper shield disposed over the first sensor, a read separation gap (RSG) disposed on the first upper shield, a second lower shield disposed over the RSG, a second sensor disposed over the second lower shield, and a second upper shield disposed over the second sensor. In some embodiments, the second lower shield comprises a CoFeHf layer. In another embodiment, the second lower shield is a synthetic antiferromagnetic multilayer comprising a first shield layer, a second shield layer, and a CoFe/Ru/CoFe anti-ferromagnetic coupling layer or a Ru layer disposed therebetween, the first and second shield layers comprising NiFe and CoFe. In yet another embodiment, the second lower shield comprises layers of Ru, IrMn, and NiFe.
    Type: Application
    Filed: July 26, 2023
    Publication date: May 2, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ming MAO, Chen-Jung CHIEN, Goncalo Marcos BAIÃO DE ALBUQUERQUE, Chih-Ching HU, Yung-Hung WANG, Ming JIANG
  • Publication number: 20240136855
    Abstract: A wireless power transfer apparatus includes a first control system, a first energy transmission system, and a second energy transmission system. The first control system is coupled to the first energy transmission system, and inputs an energy transmission signal to the first energy transmission system. The first energy transmission system is coupled to the second energy transmission system, and inputs some of the energy transmission signals obtained from the first control system into the second energy transmission system. Both the energy transmission signal obtained by the first energy transmission signal from the first control system and an energy transmission signal obtained by the second energy transmission system from the first energy transmission system supply power to a target device.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Ding Gui, Lin Hu, Deshuang Zhao, Musheng Liang, Tao Huang, Ming Zhao, Weipeng Jiang
  • Publication number: 20240136401
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material and a passivation layer is disposed on the second semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. A silicide is arranged within the passivation layer and along tops of the first doped region and the second doped region.
    Type: Application
    Filed: January 5, 2024
    Publication date: April 25, 2024
    Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
  • Publication number: 20240130022
    Abstract: This application relates to the field of lighting, and discloses an LED filament. The LED filament includes an LED chip unit, a light conversion layer, and an electrode. The light conversion layer covers the LED chip unit and part of the electrode, and a color of a light emitted by the LED filament after lighting is different from a color of the light conversion layer. This application has the characteristics of uniform light emission and good heat dissipation effect.
    Type: Application
    Filed: September 18, 2022
    Publication date: April 18, 2024
    Inventors: Tao Jiang, Lin Zhou, Ming-Bin Wang, Chih-Shan Yu, Rong-Huan Yang, Ji-Feng Xu, Heng Zhao, Jian Lu, Qi Wu
  • Patent number: 11963468
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over one or more interconnects and a diffusion barrier layer on the bottom electrode. The diffusion barrier layer has an inner upper surface that is arranged laterally between and vertically below an outer upper surface of the diffusion barrier film. The outer upper surface wraps around the inner upper surface in a top-view of the diffusion barrier layer. A data storage structure is separated from the bottom electrode by the diffusion barrier layer. A top electrode is arranged over the data storage structure.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hai-Dang Trinh, Chii-Ming Wu, Hsing-Lien Lin, Fa-Shen Jiang
  • Publication number: 20240116194
    Abstract: An integrated joint module includes a housing, a driving assembly, a speed reduction assembly, a braking assembly and an encoding assembly. The housing includes a first housing and a second housing, an annular supporting platform is arranged on an inner side of the first housing. The driving assembly includes an output shaft, a stator embedded in the annular supporting platform, and a rotor connected with the output shaft and arranged on an inner side of the stator, the speed reduction assembly and the braking assembly are connected with two ends of the output shaft. The encoding assembly is arranged on a side of the braking assembly away from the driving assembly and connected with the output shaft, the second housing is sleeved on the encoding assembly and connected with the first housing. The integrated joint module helps to simplify the structure of the joint module and reduce the cost.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 11, 2024
    Inventors: ZHONGBIN WANG, Yu Jiang, Yingbo Lei, Weizhi Ye, Lun Wang, Ming Zhang
  • Publication number: 20240116196
    Abstract: The present disclosure provides a collaborative robot arm and a joint module. The joint module includes a housing, a driving assembly, and a multi-turn absolute encoder. The joint module detects the angular position of the output shaft and records a number of rotating revolutions of the output shaft only by means of the multi-turn absolute encoder. The multi-turn absolute encoder includes a base, a bearing, a rotating shaft, an encoding disk, and a circuit board, the encoding disk is rotatably connected with the base by the rotating shaft and the bearing, the circuit board is fixedly connected with the base, and the reading head on the circuit board detects the angular position of the output shaft cooperatively with the encoding disk, making the multi-turn absolute encoder be an integrated structure. The base and the rotating shaft are detachably connected with the housing and the output shaft respectively.
    Type: Application
    Filed: January 6, 2023
    Publication date: April 11, 2024
    Inventors: Zhongbin Wang, Yu Jiang, Yingbo Lei, Weizhi Ye, Lun Wang, Ming Zhang
  • Patent number: 11952305
    Abstract: In some embodiments, a method for processing an optical fiber includes: drawing an optical fiber through a draw furnace, conveying the optical fiber through a flame reheating device downstream from the draw furnace, wherein the flame reheating device comprises one or more burners each comprising: a body having a top surface and an opposing bottom surface, an opening within the body extending from the top surface through the body to the bottom surface, wherein the optical fiber passes through the opening, and one or more gas outlets within the body; and igniting a flammable gas provided by the one or more gas outlets to form a flame encircling the optical fiber passing through the opening, wherein the flame heats the optical fiber by at least 100 degrees Celsius at a heating rate exceeding 10,000 degrees Celsius/second.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 9, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Ravindra Kumar Akarapu, Joel Patrick Carberry, David Alan Deneka, Steven Akin Dunwoody, Kenneth Edward Hrdina, John Michael Jewell, Yuanjie Jiang, Nikolaos Pantelis Kladias, Ming-Jun Li, Barada Kanta Nayak, Dale Robert Powers, Chunfeng Zhou, Vincent Matteo Tagliamonti, Christopher Scott Thomas
  • Publication number: 20240105234
    Abstract: According to the embodiments of the disclosure, a multimedia processing method, device, electronic device, and storage medium are provided by obtaining a first multimedia resource; determining an initial text content corresponding to the first multimedia resource by performing speech recognition on audio data of the first multimedia resource, the audio data of the first multimedia resource comprises speech data of the initial text content; determining an invalid text content in the initial text content, the invalid text content is semantically non-informative; determining a first playing position of speech data of the invalid text content in the first multimedia resource; and cropping the first multimedia resource based on the first playing position to obtain a second multimedia resource, wherein audio data of the second multimedia resource comprises speech data of a target text content but does not comprise the speech data of the invalid text content.
    Type: Application
    Filed: December 11, 2023
    Publication date: March 28, 2024
    Inventors: Xin Zheng, Conghui Zhu, Rui Xia, Chuxiang Shang, Dejian Zhong, Yongsen Jiang, Ming Tu, Lelai Deng
  • Publication number: 20240096930
    Abstract: Some implementations described herein include a deep trench capacitor structure and methods of formation. The deep trench capacitor structure may penetrate vertically into a silicon substrate. In some implementations, formation of the deep trench capacitor structure includes forming segments of a deep trench capacitor recess using a combination of in-situ oxidation/nitridation, ex-situ deposition, and reactive ion etching techniques. By forming the deep trench capacitor recess using the in-situ oxidation/nitridation operation, the ex-situ deposition, and the reactive ion etching techniques, a deep trench capacitor structure may be formed that meets target critical dimensions and has an aspect ratio of approximately 50:1.
    Type: Application
    Filed: April 7, 2023
    Publication date: March 21, 2024
    Inventors: Yu JIANG, Ming-Hsun LIN, Lee-Chuan TSENG
  • Publication number: 20240098271
    Abstract: An encoding method includes: a first matching block of a current block is determined; motion compensation enhancement is performed on the first matching block to obtain at least one second matching block; motion information of the current block is determined according to the at least one second matching block; and the current block is encoded according to the motion information.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Hui YUAN, Dongran JIANG, Yanhan CHU, Ye YANG, Ming LI
  • Publication number: 20240097716
    Abstract: This case is directed to supporting LB/LB, LB/MB, LB/HB and MB/HB carrier aggregation while reducing the area consumed on a transceiver and reducing power consumed on the transceiver. In some cases, four supporting such carrier aggregation may include implementing four separate radio frequency mixer chains. However, implementing four separate mixer chains may consume excessive area on the transceiver and may result in excessive transceiver power consumption. By leveraging the fact that HB LO frequency ranges overlap with LB LO frequency ranges, a dual-band gain stage may be implemented such that an LB/HB mixer may share a single LO signal (e.g., so as to provide a dual-band matching network that may provide impedance matching at LB and HB frequencies) without extending an original LB LO signal bandwidth. The dual-band gain stage may reduce space and power consumed on the transceiver while maintaining support for LB/LB, LB/MB, LB/HB and MB/HB carrier aggregation.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Haowei Jiang, Ming-Da Tsai
  • Publication number: 20240097715
    Abstract: This case is directed to supporting LB/LB, LB/MB, LB/HB and MB/HB carrier aggregation while reducing the area consumed on a transceiver and reducing power consumed on the transceiver. In some cases, four supporting such carrier aggregation may include implementing four separate radio frequency mixer chains. However, implementing four separate mixer chains may consume excessive area on the transceiver and may result in excessive transceiver power consumption. By leveraging the fact that HB LO frequency ranges overlap with LB LO frequency ranges, a dual-band gain stage may be implemented such that an LB/HB mixer may share a single LO signal (e.g., so as to provide a dual-band matching network that may provide impedance matching at LB and HB frequencies) without extending an original LB LO signal bandwidth. The dual-band gain stage may reduce space and power consumed on the transceiver while maintaining support for LB/LB, LB/MB, LB/HB and MB/HB carrier aggregation.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Haowei Jiang, Ming-Da Tsai
  • Patent number: 11933459
    Abstract: A lamp including electrical leads extending into a supporting stem that are in communication with a base electrode for engagement to a light fixture; and a light engine comprising light emitting diode filaments that are in electrical communication with the electrical leads. The light emitting diode filaments including a circuit having a plurality of contact pads arranged along a length of a substrate. The light emitting diode filaments further include light emitting diode (LED) chips engaged to the contact pads along the length of the substrate to provide that the light emitting diode (LED) chips are electrically connected in series. In some embodiments, each light emitting diode (LED) chip includes at least a light transmission surface that is in contact with an individual portion of phosphor for the LED chip. In other embodiments, a phosphor layer extends over an island of LED chips.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: March 19, 2024
    Assignee: LEDVANCE LLC
    Inventors: Xingrong Wang, Tianzheng Jiang, Ming Li
  • Publication number: 20240089231
    Abstract: Example chat interface creation method and apparatus are described. One example method includes displaying a first group chat interface on a touchscreen of an electronic device. The electronic device receives a first operation in the first group chat interface, and displaying displays a second group chat interface based on the first operation. The first group chat interface is a chat interface of a first chat group, and the first chat group includes a first user who enters the first group chat interface on the electronic device. The second group chat interface is a chat interface of a second chat group, and both the second chat group and the first chat group include the first user.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Ming JIANG, Feng LIU
  • Patent number: 11926935
    Abstract: An automatic yarn feeding system is provided. The system comprises a yarn feeding track which is arranged on the twisting machine in a length direction of the twisting machine and provided with a yarn feeding manipulator walking along the yarn feeding track; and a supply zone which is arranged on one side of the yarn feeding track and used to buffer base yarns. The yarn feeding manipulator is used to convey the base yarns from the supply zone to a yarn feeding creel of each spindle position. The yarn feeding track is located in the middle of the top of the twisting machine. The supply zone is provided with a structure for buffering a plurality of base yarns, and is located on one side of an end of the yarn feeding track on the top of a control cabinet.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: March 12, 2024
    Assignee: YICHANG JINGWEI TEXTILE MACHINERY CO., LTD.
    Inventors: Pihua Zhang, Ming Xiao, Yongming Li, Haibo Jiang, Ming Zhang, Huanian Yang
  • Patent number: 11924080
    Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 5, 2024
    Assignee: VMware LLC
    Inventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
  • Patent number: D1017882
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: March 12, 2024
    Assignee: JIAXING SUPER LIGHTING ELECTRIC APPLIANCE CO., LTD
    Inventors: Tao Jiang, Ming-Bin Wang, Chen-Kun Chen, Dong-Mei Zhang