Patents by Inventor Ming-Jung Chen
Ming-Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955484Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.Type: GrantFiled: June 10, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
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Publication number: 20240077196Abstract: A lamp structure of an umbrella contains a body, an illumination device, and a control pusher. The body includes a shaft, a notch, a runner slidably, and multiple stretchers. The illumination device includes at least one lighting element, a circuit board, and a battery. The circuit board has a control switch, when the runner is moved upward to push the illumination device, the umbrella is opened. The control pusher is connected to the runner and includes a controlling element. The control pusher is slid vertically with respect to the shaft and is switched in three-section positions, such that the control pusher is slid to a first position, a second position, and a third position relative to the shaft to drive the control switch to be conducted or not so that the circuit board controls the at least one lighting element to power on or off.Type: ApplicationFiled: August 22, 2023Publication date: March 7, 2024Inventors: SHUN-JUNG CHEN, SUN-FENG SUNG, MING-HSIUNG CHEN
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Publication number: 20200316654Abstract: A method of processing a substrate in semiconductor fabrication is provided. The method includes supplying a mixture from a storage module to a chamber via an inlet conduit. The method further includes detecting the concentration of a substance in the mixture. The method also includes dispensing the mixture over a substrate disposed in the chamber. In addition, the method includes supplying a supply solution including the substance to the chamber via the inlet conduit and dispensing the supply solution over the substrate when the concentration of the substance in the mixture is less than a desired value. The supply solution is supplied to the inlet conduit at a first position that is at a portion of the inlet conduit extending in the chamber.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Inventors: Chun-Syuan JHUAN, Ming-Jung CHEN, Shao-Yen KU, Tsai-Pao SU
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Patent number: 10780461Abstract: A method of processing a substrate in semiconductor fabrication is provided. The method includes supplying a mixture to a process module. The method further includes detecting the concentration of a substance in the mixture. The method also includes dispensing the mixture over a substrate in the process module. In addition, the method includes supplying a supply solution including the substance to the process module and dispensing the supply solution over the substrate if the concentration of the substance in the mixture is less than a desired value.Type: GrantFiled: May 29, 2015Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Chun-Syuan Jhuan, Ming-Jung Chen, Shao-Yen Ku, Tsai-Pao Su
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Patent number: 9997384Abstract: An apparatus comprises a process chamber, and a loadlock connected to the process chamber. The loadlock is configured to have a wafer holder disposed therein. The wafer holder is configured to store a plurality of wafers, and is configured to transport the plurality of wafers away from the loadlock.Type: GrantFiled: December 1, 2011Date of Patent: June 12, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Yen Ku, Ming-Jung Chen, Tzu Yang Chung, Chi-Yun Tseng, Rui-Ping Chuang
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Patent number: 9895949Abstract: A retractable suspension system for use with an amphibious vehicle is provided and includes three rotation points disposed on the vehicle body of the vehicle, three integration points disposed on an integration element of a tire, an actuating device and a damping component, so as to render the retractable suspension system structurally simple and multifunctional.Type: GrantFiled: December 29, 2015Date of Patent: February 20, 2018Assignee: SHIP AND OCEAN INDUSTRIES R&D CENTERInventors: Ting-Yu Lu, Chai-Min Chiang, Ming-Jung Chen, Chen-Chou Lin, Jyh-Jone Lee
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Publication number: 20170158014Abstract: A retractable suspension system for use with an amphibious vehicle is provided and includes three rotation points disposed on the vehicle body of the vehicle, three integration points disposed on an integration element of a tire, an actuating device and a damping component, so as to render the retractable suspension system structurally simple and multifunctional.Type: ApplicationFiled: December 29, 2015Publication date: June 8, 2017Inventors: TING-YU LU, CHAI-MIN CHIANG, MING-JUNG CHEN, CHEN-CHOU LIN, JYH-JONE LEE
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Patent number: 9601360Abstract: A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.Type: GrantFiled: March 16, 2015Date of Patent: March 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jyun-Chao Chen, Ming-Jung Chen, Shao-Yen Ku, Tsai-Pao Su
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Publication number: 20160336200Abstract: A method of processing a substrate in semiconductor fabrication is provided. The method includes supplying a mixture to a process module. The method further includes detecting the concentration of a substance in the mixture. The method also includes dispensing the mixture over a substrate in the process module. In addition, the method includes supplying a supply solution including the substance to the process module and dispensing the supply solution over the substrate if the concentration of the substance in the mixture is less than a desired value.Type: ApplicationFiled: May 29, 2015Publication date: November 17, 2016Inventors: Chun-Syuan JHUAN, Ming-Jung CHEN, Shao-Yen KU, Tsai-Pao SU
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Publication number: 20160276186Abstract: A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Jyun-Chao CHEN, Ming-Jung CHEN, Shao-Yen KU, Tsai-Pao SU
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Publication number: 20130142594Abstract: An apparatus comprises a process chamber, and a loadlock connected to the process chamber. The loadlock is configured to have a wafer holder disposed therein. The wafer holder is configured to store a plurality of wafers, and is configured to transport the plurality of wafers away from the loadlock.Type: ApplicationFiled: December 1, 2011Publication date: June 6, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shao-Yen Ku, Ming-Jung Chen, Tsu-Yang Chung, Chi-Yun Tseng, Jui-Ping Chuang
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Patent number: 7773409Abstract: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.Type: GrantFiled: December 12, 2007Date of Patent: August 10, 2010Assignee: Industrial Technology Research InstituteInventors: Ming-Jung Chen, Te-Sheng Chao, Philip H. Yeh
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Patent number: 7660147Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.Type: GrantFiled: December 18, 2007Date of Patent: February 9, 2010Assignees: Industrial Technology Research Institute, Powerchip Semiconductor Corp., Nany Technology Corporation., Promos Technologies Inc., Winbond Electronics Corp.Inventors: Te-Sheng Chao, Ming-Jung Chen, Philip H. Yeh, Ming-Jinn Tsai
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Publication number: 20080219046Abstract: A writing method for a phase change memory is disclosed. The writing method inputs a first writing pulse signal to a phase change memory to heat the phase change memory to above a first temperature and inputting a second writing pulse signal to the phase change memory to keep the phase change memory at a second temperature.Type: ApplicationFiled: December 12, 2007Publication date: September 11, 2008Inventors: Ming-Jung Chen, Te-Sheng Chao, Philip H. Yeh
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Publication number: 20080151613Abstract: A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase change memory and providing a second crystallization current pulse to the phase change memory. The first crystallization current pulse has a first rising edge, a first falling edge and a first peak current held for a first hold time. The second crystallization current pulse has a second peak current. The second peak current follows the first falling edge and is held for a second hold time.Type: ApplicationFiled: December 18, 2007Publication date: June 26, 2008Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, POWERCHIP SEMICONDUCTOR CORP., NANYA TECHNOLOGY CORPORATION, PROMOS TECHNOLOGIES INC., WINBOND ELECTRONICS CORP.Inventors: Te-Sheng Chao, Ming-Jung Chen, Philip H. Yeh, Ming-Jinn Tsai
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Patent number: D390314Type: GrantFiled: February 11, 1997Date of Patent: February 3, 1998Inventor: Ming-Jung Chen