Patents by Inventor Ming Pan
Ming Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240172434Abstract: A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.Type: ApplicationFiled: January 31, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Patent number: 11988507Abstract: Disclosed are a calculation method and an installation mechanism for compressor unit single meter alignment pad iron adjustment. The installation mechanism includes: a bracket and a connecting piece installed on the bracket; and an installation piece arranged on an end portion of the bracket. The bracket is provided with an installation box, the installation box is internally and rotatably provided with a rolling rod, the rolling rod is winded with a connecting rope, one end, away from the rolling rod, of the connecting rope is provided with a fixing piece, one end of the rolling rod extends to an outer side of the installation box and is connected with a cam, the cam is provided with a groove, the installation box is provided with a limiting piece, one side, towards the cam, of the limiting piece is provided with an open slot.Type: GrantFiled: December 6, 2023Date of Patent: May 21, 2024Assignee: CHINA NATIONAL CHEMICAL ENGINEERING THIRD CONSTRUCTION CO., LTDInventors: Jiahui Fu, Xinyu Pan, Chengkang Han, Ming'ao Wu, Guohua Cheng, Wenwei Li
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Publication number: 20240157415Abstract: A process for producing a heavy metal mediated biochar composite using silicate solidification. Hydrocharis dubia has excellent enrichment of manganese ions in sewage, and is used to treat sewage water to adsorb heavy metals such as lead, manganese and zinc contained in the sewage water into roots, stems and leaves thereof, which are pyrolysed in stages at high temperature with activated red mud and bentonite prior to blending with zeolites, to produce said heavy metal mediated biochar composite; the process significantly extends the migration time of heavy metals, increases the stability of heavy metals and reduces the risk of environmental pollution by heavy metal leakage.Type: ApplicationFiled: March 3, 2022Publication date: May 16, 2024Applicant: CHINESE RESEARCH ACADEMY OF ENVIRONMENTAL SCIENCESInventors: Lei WANG, Beidou XI, Xiaoshu WANG, Nan XU, Yan SHAO, Shaofeng LI, Yangyang WANG, Jinsheng WANG, Ming CHANG, Gen ZHANG, Lulu PAN, Honghu ZENG, Bo YANG
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Patent number: 11983363Abstract: A user gesture behavior simulation system includes a touch gesture recording and editing device and a touch gesture simulation device. When at least one touch gesture is implemented on a record touch object with at least one finger of a user, the at least one touch gesture is recorded by the touch gesture recording and editing device, and at least one touch gesture operating trajectory is correspondingly generated by the touch gesture recording and editing device. The touch gesture simulation device includes at least one artificial finger. The at least one artificial finger is driven and moved to an under-test touch object by the touch gesture simulation device. The at least one touch gesture is simulated by the touch gesture simulation device according to the at least one touch gesture operating trajectory.Type: GrantFiled: September 5, 2023Date of Patent: May 14, 2024Assignee: PRIMAX ELECTRONICS LTD.Inventors: Yung-Tai Pan, Jui-Hung Hsu, Chang-Ming Huang
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Patent number: 11979025Abstract: A dual-mode combined control method for a multi-inverter system based on a double split transformer is provided. For an extremely-weak grid, the method provides the dual-mode combined control method for a multi-inverter system based on a double split transformer. According to the method, the equivalent grid impedance at a point of common coupling (PCC) of one grid-connected inverter (GCI) in the multi-inverter system based on the double split transformer is obtained with a grid impedance identification algorithm, and the system sequentially operates in a full current source mode, a hybrid mode, and a full voltage source mode according to a gradually increasing equivalent grid impedance, thereby effectively improving the stability of the multi-inverter system based on the double split transformer during variation of the strength of the grid. The method ensures that the system can still operate stably in the extremely-weak grid.Type: GrantFiled: May 13, 2021Date of Patent: May 7, 2024Assignee: HEFEI UNIVERSITY OF TECHNOLOGYInventors: Xing Zhang, Ming Li, Zixuan Guo, Jilei Wang, Hailong Pan, Yang Wang, Qian Gao, Fei Li
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Publication number: 20240139790Abstract: A composite biochar for controlling heavy metal pollution and a process for producing the same, in particular enrichment of heavy metals such as arsenic and lead in soil with centipede grass, thereafter centipede grass is sintered with hydroxyapatite, sepiolite and chitosan, and compounded with microorganisms to produce said composite biochar; through the process of the present invention, heavy metals such as arsenic and lead are stably enriched or coated in said composite biochar, significantly reducing the potential hazard of arsenic and lead to the environment, and also providing new developmental ideas for treating heavy metal biomass.Type: ApplicationFiled: March 16, 2022Publication date: May 2, 2024Applicant: CHINESE RESEARCH ACADEMY OF ENVIRONMENTAL SCIENCESInventors: Lei WANG, Beidou XI, Yangyang WANG, Yan SHAO, Nan XU, Shaofeng LI, Xiaoshu WANG, Jinsheng WANG, Ming CHANG, Gen ZHANG, Lulu PAN, Kui ZHANG, Honghu ZENG
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Publication number: 20240140843Abstract: A porous biochar for improving heavy pollution and a method for producing the same. Said porous biochar is prepared as follows: arrowhead, which has excellent enrichment of lead, is used to absorb heavy metal lead in polluted water or artificial wetlands, simultaneously absorb heavy metal cadmium, thereafter is dried and treated as a biomass, and then the biomass is calcined in stages with a passivating agent in a high temperature environment, so as to heavy metals such as lead and cadmium be stably coated or enriched in a biochar, which is mixed with Pseudomonas aeruginosa having high resistant, to obtain the porous biochar; the porous biochar has high specific surface area, high porosity and excellent mechanical properties, is very stable under different acid-base environments and oxidizing conditions.Type: ApplicationFiled: February 23, 2022Publication date: May 2, 2024Applicant: CHINESE RESEARCH ACADEMY OF ENVIRONMENTAL SCIENCESInventors: Lei WANG, Beidou XI, Honghu ZENG, Nan XU, Yan SHAO, Shaofeng LI, Ming CHANG, Jinsheng WANG, Xiaoshu WANG, Yangyang WANG, Gen ZHANG, Lulu PAN, Jing WANG
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Publication number: 20240147338Abstract: A method for optimizing CHO configuration information includes sending, by a source network side device, CHO configuration information to a terminal; receiving, by the source network side device, first indication information, where the first indication information includes an RLF report; and optimizing, by the source network side device, CHO configuration information corresponding to the terminal according to the first indication information.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: Ming Wen, Xiang Pan, Boubacar Kimba Dit Adamou
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Patent number: 11967172Abstract: A device includes a touch-mode biometric sensor having a first side facing toward a user and a second side opposite to the first side, and a display arranged under the touch-mode biometric sensor and adjacent to the second side and configured to display an image in response to a sensing result, associated with a biometric feature of the user, of the touch-mode biometric sensor.Type: GrantFiled: June 1, 2021Date of Patent: April 23, 2024Assignee: IMAGE MATCH DESIGN INC.Inventors: Chia-Ming Wu, Yan-Quan Pan, Yen-Kuo Lo, Yeh-Suan Yan
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Patent number: 11966133Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.Type: GrantFiled: May 18, 2023Date of Patent: April 23, 2024Assignee: INNOLUX CORPORATIONInventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240102588Abstract: A quick connection clamping hoop, including an upper clamping hoop body and a lower clamping hoop body that are both in a semi-annular shape; where the upper clamping hoop body and the lower clamping hoop body each have one end as a plug connecting end and the other end as a connecting end; connecting ends of the upper clamping hoop body and the lower clamping hoop body each are provided with a lug, and the connecting ends of the two are connected together via a bolt passing through lugs; plug connecting ends of the two are connected together via a plug connecting mechanism disposed at the plug connecting ends of the two. A clamping hoop in this structure is assembled and connected to a pipe quickly, and is convenient for use, which can greatly improve production efficiency of the clamping hoop and efficiency of pipe connection.Type: ApplicationFiled: December 7, 2023Publication date: March 28, 2024Inventors: Tonghu ZHANG, Chengfei PAN, Ming LI
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Publication number: 20240097027Abstract: A semiconductor structure includes a semiconductor substrate, first to third isolation structures, and a conductive feature. The first to third isolation structures are over the semiconductor substrate and spaced apart from each other. The semiconductor substrate comprises a region surrounded by a sidewall of the first isolation structure and a first sidewall of the second isolation structure. The conductive feature extends vertically in the semiconductor substrate and between the between the second and third isolation structures, wherein the conductive feature has a rounded corner adjoining a second sidewall of the second isolation structure opposite the first sidewall of the second isolation structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ming PAN, Chia-Ta HSIEH, Po-Wei LIU, Yun-Chi WU
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Patent number: 11924080Abstract: Some embodiments provide a method of identifying packet latency in a software defined datacenter (SDDC) that includes a network and multiple host computers executing multiple machines. At a first host computer, the method identifies and stores (i) multiple time values associated with several packet processing operations performed on a particular packet sent by a first machine executing on the first host computer, and (ii) a time value associated with packet transmission through the SDDC network from the first host computer to a second host computer that is a destination of the particular packet. The method provides the stored time values to a set of one or more controllers to process to identify multiple latencies experienced by multiple packets processed in the SDDC.Type: GrantFiled: March 21, 2022Date of Patent: March 5, 2024Assignee: VMware LLCInventors: Haoran Chen, Ming Shu, Xi Cheng, Feng Pan, Xiaoyan Jin, Caixia Jiang, Qiong Wang, Qi Wu
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Patent number: 11925017Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.Type: GrantFiled: January 13, 2020Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Chia-Ming Pan, Hsin-Chi Chen
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Publication number: 20240071722Abstract: Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Sheng-Liang Pan, Bing-Hung Chen, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang, Jack Kuo-Ping Kuo
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Publication number: 20240072170Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes a metal gate structure, over the semiconductor fin, that is sandwiched at least by the first spacers. The semiconductor device includes a gate electrode contacting the metal gate structure. An interface between the metal gate structure and the gate electrode has its side portions extending toward the semiconductor fin with a first distance and a central portion extending toward the semiconductor fin with a second distance, the first distance being substantially less than the second distance.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Yih-Ann Lin, Chia Ming Liang, Ryan Chia-Jen CHEN
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Publication number: 20240072155Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Inventors: Kuo-Hua Pan, Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh, Java Wu
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Patent number: D1018343Type: GrantFiled: December 29, 2020Date of Patent: March 19, 2024Assignee: BEIJING VOYAGER TECHNOLOGY CO., LTD.Inventors: Anan Pan, Ming-hui Wu, Youmin Wang
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Patent number: D1023651Type: GrantFiled: November 19, 2020Date of Patent: April 23, 2024Assignee: MACHAN INTERNATIONAL CO., LTD.Inventor: Kuei Ming Pan