Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

Abstract: This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.

Abstract: A computer system includes an integrated core and graphic controller device having a core logic controller portion and a graphic controller portion, a system memory pool, and a stand-alone frame buffer memory pool separate from the system memory pool. A first memory data bus interconnects the integrated core and graphic controller device and the system memory pool. A second memory data bus interconnects the integrated core and graphic controller device and the frame buffer memory pool. A memory address and control signal bus interconnects the integrated core and graphic controller device, the system memory pool and the frame buffer memory pool.