Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: A frequency-modulated carrier receiver includes a signal extractor and an injection-locked oscillator. The signal extractor is configured to operably receive a frequency-modulated carrier and generate an injection signal based on the frequency-modulated carrier, so that the injection signal has a relatively smaller frequency variation than the frequency-modulated carrier. The injection-locked oscillator is coupled with the signal extractor and configured to operably filter out noise components in the injection signal to generate an output signal.

Abstract: A process, voltage, and temperature compensated oscillator, formed on an integrate circuit implemented by a semiconductor process, receives a supply voltage and includes: a variation bias unit provided with a variation bias output terminal and generating a process, voltage, and temperature compensated signal; a controlled oscillating unit provided with a control input terminal and an oscillating output and determining a signal oscillating frequency at the oscillating output terminal according to a signal at the control input terminal; and a tuning unit provided with a tuning input terminal, a compensating input terminal, a control output terminal, and a variable-parameter element, wherein the variable-parameter element includes a parameter and is coupled to the control output terminal, and the tuning unit determines the parameter according to a signal at the variation bias output terminal and a voltage signal or a digital signal received at the tuning input terminal.

Abstract: A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.

Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.

Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.

Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Abstract: Method and associated apparatus of data extraction, including: sampling a signal and obtaining a plurality of sampled values, providing a reference sample quantity when the sampled values transit, providing a unit bit sample quantity according to the reference sample quantity, and corresponding each of the sampled values to each data bit of the signal according to the unit bit sample quantity.

Abstract: A frequency locking method, for locking an output signal outputted from a frequency locking circuit to a target frequency, comprising: (a) detecting an output frequency of the output signal, wherein the output signal is generated according to an oscillating frequency of a controllable oscillator; (b) computing a frequency difference between the output frequency and the target frequency; (c) utilizing a controllable factor adjusting device to provide and to adjust a normalization factor according to the frequency difference, to anticipate a gain of the controllable oscillator and to provide a control signal related with the normalization factor and the frequency difference, wherein the output frequency is related with a product of the normalization factor and the gain of the controllable oscillator; and (d) controlling the controllable oscillator according to the control signal, such that the output frequency approaches to the target frequency.

Abstract: A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

Abstract: A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.

Abstract: A delay-locked loop (DLL) which receives a reference clock signal and outputs an output clock signal is provided. The DLL includes a phase detector, a delay chain, an anti-false lock (AFL) circuit, and a loop filter. The phase detector outputs a first comparison signal according to a phase comparison between the reference clock signal and the output clock signal. The delay chain generates a plurality of strobe clock signals and the output clock signal by delaying the reference clock signal for different intervals. The AFL circuit outputs a second comparison signal according to a phase comparison between the reference clock signal and the strobe clock signals. The loop filter controls the delay time of the output clock signal according to the first and the second comparison signals in order to lock the delay time of the output clock signal at a preset value.

Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Abstract: A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

Abstract: A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.

Abstract: A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path.

Abstract: A clock and data recovery circuit includes a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider. The voltage-controlled oscillator includes a current mirror, a control circuit, a current modulation module and a current-controlled oscillator. The current mirror has a current-controlling path and a current-outputting path. The current-controlling path and the current-outputting path are in a proportional relationship. The control circuit is used for adjusting the current flowing through the current-controlling path according to the control voltage. The current modulation module is used for generating a differential current according to the judging signal. The current-controlled oscillator is used for adjusting the phase of the second output clock signal according to the sum of the differential current and the current flowing through the current-outputting path.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.

Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.

Abstract: A timing-signal generator includes a PLL circuit, one or more rising/falling edge generating unit and one or more timing-signal generating unit. In response to a reference signal with a frequency Fref, the PLL outputs M voltage controlled signals with the same frequency Fvco=N*Fref and equally distributed phase differences. The rising/falling edge generating unit is for generating a rising point signal and a falling point signal corresponding to respective ones one of M*P candidate timing points which are defined in a cycle of the reference signal according to the M voltage controlled signals. The timing-signal generating unit coupled to the rising/falling edge generating unit is for generating a timing signal which toggles high in response to the rising point signal and toggles low in response to the falling point signal.