Abstract: The present disclosure provides a radar object recognition method, which includes steps as follows. The radar image generation is performed on radar data to generate a radar image; the radar image is inputted into an object recognition model, so that the object recognition model outputs a recognition result; the post-process is performed on the recognition result to eliminate recognition errors from the recognition result.

Abstract: In an embodiment, a structure includes: a first integrated circuit die including first die connectors; a first dielectric layer on the first die connectors; first conductive vias extending through the first dielectric layer, the first conductive vias connected to a first subset of the first die connectors; a second integrated circuit die bonded to a second subset of the first die connectors with first reflowable connectors; a first encapsulant surrounding the second integrated circuit die and the first conductive vias, the first encapsulant and the first integrated circuit die being laterally coterminous; second conductive vias adjacent the first integrated circuit die; a second encapsulant surrounding the second conductive vias, the first encapsulant, and the first integrated circuit die; and a first redistribution structure including first redistribution lines, the first redistribution lines connected to the first conductive vias and the second conductive vias.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit.

Abstract: An image processing circuit turns off the writing unit of the controller of the DRAM when the previous frame is identical to the current frame. In this way, the writing unit of the controller of the DRAM does not write the current frame into the DRAM, thereby reducing power consumption.

Abstract: A method for generating an over-drive grey level for driving a pixel includes providing a corresponding over-drive function according to an original grey level for the pixel in the previous frame, and generating the over-drive grey level according to the corresponding over-drive function and the original grey level for the pixel in the current frame.

Abstract: A timing control circuit with a power-saving function includes a receiving circuit, a processor, and a first switch. The receiving circuit receives a first set of differential signals for generating a set of command signals. The processor is coupled to the receiving circuit and generates a first control signal according to the set of command signals. The switch is coupled between the receiving circuit and the processor for selectively decoupling the receiving circuit from a first power supply according to the first control signal.

Abstract: A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit.

Abstract: A noisy signal analysis in which a threshold value is set to evaluate the presentation of the display device. The analysis can produce the range of noise level of the image for measuring the distortion block of image caused by the display devices. Furthermore, the apparatus includes a step function generator for producing step functions, a transforming unit for changing threshold value in step functions, and a display for showing the image corresponding to both the high value and low value.

Abstract: The invention discloses a gamma image correction method and device that employs an improved interpolating operation, comprising receiving an original image data point; retrieving p conversion values (p is larger than 2) from a memory unit according to the original image data point; and arithmetically processing the p conversion values for generating a gamma corrected image parameter value from the original image data point wherein the original image data point is a N bits data, the memory unit contains 2k conversion values and N is lager than k.

Abstract: An image processing circuit turns off the writing unit of the controller of the DRAM when the previous frame is identical to the current frame. In this way, the writing unit of the controller of the DRAM does not write the current frame into the DRAM, thereby reducing power consumption.

Abstract: A symbol-sharing differential pulse code modulation (DPCM) encoder is disclosed. Since the bit widths of DPCM encoded data are truncated in hardware to avoid overflow and symbols are shared in software, the DPCM encoded data have the same number of symbols as original input data do, which effectively reduces symbol lengths and average code length of the output data generated by a Huffman encoder at a rear stage.

Abstract: A method for generating an over-drive grey level for driving a pixel includes providing a corresponding over-drive function according to an original grey level for the pixel in the previous frame, and generating the over-drive grey level according to the corresponding over-drive function and the original grey level for the pixel in the current frame.

Abstract: A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.

Abstract: An overdrive apparatus for advancing the response time of a liquid crystal display (LCD) is disclosed, comprising a overdrive table, a memory storage, and a determining device, wherein the overdrive table is used for saving a plurality of overdrive-voltage values, the memory storage is used for saving a first frame, the determining device receives a first pixel, which is corresponding with a second pixel of the first frame, wherein the determining device can select an overdrive-voltage value from the overdrive table according to the first pixel and the second pixel, wherein the memory storage is provided within a first chipset, which comprises a first active face and a plurality of first bond pads provided on the first active face; the determining device is provided within a second chipset, which comprises a second active face and a plurality of second bond pads provided on the second active face, wherein the first chipset and the second chipset are stacked with each other, and the second bond pads are electr

Abstract: A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y.

Abstract: A timing control circuit with a power-saving function includes a receiving circuit, a processor, and a first switch. The receiving circuit receives a first set of differential signals for generating a set of command signals. The processor is coupled to the receiving circuit and generates a first control signal according to the set of command signals. The switch is coupled between the receiving circuit and the processor for selectively decoupling the receiving circuit from a first power supply according to the first control signal.

Abstract: The invention discloses a method for detecting resolution and a timing controller. The method includes following steps: first, receiving a set of image control signals; judging resolution of image data. Wherein, the resolution of the image data includes a resolution of first dimension and a resolution of second dimension. The timing controller receives image data and a set of image control signals. The timing controller includes a resolution detecting circuit and a timing control unit.

Abstract: The invention discloses a gamma image correction method and device that employs an improved interpolating operation, comprising receiving an original image data point; retrieving p conversion values (p is larger than 2) from a memory unit according to the original image data point; and arithmetically processing the p conversion values for generating a gamma corrected image parameter value from the original image data point wherein the original image data point is a N bits data, the memory unit contains 2k conversion values and N is lager than k.