Patents by Inventor Ming-Sung Tsai
Ming-Sung Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Publication number: 20240178091Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: ApplicationFiled: February 7, 2024Publication date: May 30, 2024Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
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Patent number: 11996227Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.Type: GrantFiled: December 13, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
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Patent number: 11959606Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.Type: GrantFiled: March 30, 2021Date of Patent: April 16, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chen-Hsiu Lin, Cheng-Ying Lee, Ming-Sung Tsai
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Patent number: 11935804Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
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Patent number: 11935871Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.Type: GrantFiled: August 30, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
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Publication number: 20210301993Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.Type: ApplicationFiled: March 30, 2021Publication date: September 30, 2021Inventors: CHEN-HSIU LIN, CHENG-YING LEE, MING-SUNG TSAI
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Patent number: 8833966Abstract: A light device and its light emitting diode module are provided in the disclosure. The light emitting diode module includes a substrate, an arrayed light emitting group and a single sealant body. The arrayed light emitting group includes a plurality of light emitting strings connected between a positive pole and a negative pole in parallel. Each light emitting strings includes a plurality of blue light emitting diode chips and a red light emitting diode chips, which are both electrically connected on the substrate in series. The single sealant body completely covers all of the light emitting strings, and is contained with phosphors uniformly therein.Type: GrantFiled: September 14, 2012Date of Patent: September 16, 2014Assignee: Edison Opto CorporationInventors: Ming-Zhe Hsieh, An-Yu Hsieh, Ming-Sung Tsai
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Publication number: 20130258653Abstract: A light device and its light emitting diode module are provided in the disclosure. The light emitting diode module includes a substrate, an arrayed light emitting group and a single sealant body. The arrayed light emitting group includes a plurality of light emitting strings connected between a positive pole and a negative pole in parallel. Each light emitting strings includes a plurality of blue light emitting diode chips and a red light emitting diode chips, which are both electrically connected on the substrate in series. The single sealant body completely covers all of the light emitting strings, and is contained with phosphors uniformly therein.Type: ApplicationFiled: September 14, 2012Publication date: October 3, 2013Applicant: EDISON OPTO CORPORATIONInventors: Ming-Zhe HSIEH, An-Yu HSIEH, Ming-Sung TSAI
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Publication number: 20100321913Abstract: A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.Type: ApplicationFiled: August 26, 2010Publication date: December 23, 2010Applicant: UTAC (TAIWAN) CORPORATIONInventors: Ming-Sung Tsai, Hsieh-Wei Hsu
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Patent number: 7795077Abstract: A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.Type: GrantFiled: October 31, 2007Date of Patent: September 14, 2010Assignee: UTAC (Taiwan) CorporationInventors: Ming-Sung Tsai, Hsieh-Wei Hsu
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Publication number: 20080273299Abstract: A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield.Type: ApplicationFiled: October 31, 2007Publication date: November 6, 2008Applicant: United Test Center Inc.Inventors: Ming-Sung Tsai, Hsieh-Wei Hsu
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Patent number: 7122407Abstract: A method for fabricating a window ball grid array (WBGA) semiconductor package is provided. A substrate is prepared having a through opening and ball pads on a lower surface thereof. A chip is mounted over the opening of the substrate via an adhesive, with gaps not applied with the adhesive left between the chip and substrate. The chip is electrically connected to the substrate via bonding wires through the opening. A spacer is attached to the lower surface of the substrate and has a through hole and a recessed portion around the through hole. During molding, the spacer is clamped between the substrate and a mold, and the recessed portion is located between the ball pads and the opening, such that a resin material for forming an encapsulation body encapsulates the chip and flows through the gaps to encapsulate the bonding wires. The recessed portion holds resin flash therein.Type: GrantFiled: August 24, 2004Date of Patent: October 17, 2006Assignee: Ultra Tera CorporationInventors: Sung-Jin Kim, Chih-Horng Horng, Ming-Sung Tsai, Chung-Ta Yang
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Patent number: 7080447Abstract: A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.Type: GrantFiled: March 16, 2004Date of Patent: July 25, 2006Assignee: Ultratera CorporationInventors: Chong-Ren Maa, Wan-Kuo Chih, Ming-Sung Tsai
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Publication number: 20060027901Abstract: A stacked chip package with exposed lead-frame bottom surface is disclosed. The stacked chip package includes a first die encapsulated in an encapsulated molding compound, which is mounted on an active surface of a second die. A bottom surface of the second die is mounted to a top surface of a die supporting section of the lead-frame. The bottom surface of the die supporting section is exposed outside the encapsulated molding compound. A plurality of bonding wires electrically interconnect the die pads of the first die and the second die to the corresponding lead fingers. Moreover, each lead finger of the lead-frame is preferably formed with a deflected structure with a bent section, which enables the dimension size of the stacked chip package to get more compact.Type: ApplicationFiled: August 9, 2004Publication date: February 9, 2006Inventors: Ming-Sung Tsai, Jin-Ho Kim, Eul-Chul Jang
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Publication number: 20050208707Abstract: A method for fabricating a window ball grid array (WBGA) semiconductor package is provided. A substrate is prepared having a through opening and ball pads on a lower surface thereof. A chip is mounted over the opening of the substrate via an adhesive, with gaps not applied with the adhesive left between the chip and substrate. The chip is electrically connected to the substrate via bonding wires through the opening. A spacer is attached to the lower surface of the substrate and has a through hole and a recessed portion around the through hole. During molding, the spacer is clamped between the substrate and a mold, and the recessed portion is located between the ball pads and the opening, such that a resin material for forming an encapsulation body encapsulates the chip and flows through the gaps to encapsulate the bonding wires. The recessed portion holds resin flash therein.Type: ApplicationFiled: August 24, 2004Publication date: September 22, 2005Inventors: Sung-Jin Kim, Chih-Horng Horng, Ming-Sung Tsai, Chung-Ta Yang
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Patent number: 6933448Abstract: A printed circuit board having a permanent solder mask includes a substrate made of a glassfiber reinforced epoxy resin material. The top and bottom surfaces of the substrate are disposed thereon a conductive pattern respectively. An epoxy resin solder mask is coated on each surface of the substrate in such a way that the conductive pattern is divided into a sheltered portion covered by the solder mask and an unsheltered portion exposed outside. The solder mask also has an even and smooth outer surface with a micro-roughness ranging between 0.5 ?m˜10 ?m and an optimum thickness ranging between 2 ?m˜200 ?m.Type: GrantFiled: January 16, 2004Date of Patent: August 23, 2005Assignee: S & S Technology CorporationInventors: Chong-Ren Maa, Wan-Kuo Chih, Ming-Sung Tsai
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Publication number: 20040172818Abstract: A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.Type: ApplicationFiled: March 16, 2004Publication date: September 9, 2004Applicant: S & S Technology CorporationInventors: Chong-Ren Maa, Wan-Kuo Chih, Ming-Sung Tsai
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Patent number: D636355Type: GrantFiled: May 12, 2010Date of Patent: April 19, 2011Assignee: Edison Opto CorporationInventors: Ming-Sung Tsai, Hou-Kun Lin
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Patent number: D637564Type: GrantFiled: October 19, 2010Date of Patent: May 10, 2011Assignee: Edison Opto CorporationInventors: Chung-Ting Tseng, Ming-Sung Tsai, Shih-Tai Chuang