Abstract: A read clock interface includes a serial-to-parallel converter for receiving two interleaved serial data streams read out from a disk and converting the serial data to 17-bit parallel data, and a state machine for receiving a clock signal having a frequency one-half that of a frequency at which the serial data is read out from the disk and frequency dividing the clock signal to generate a conversion clock signal consisting of alternating conversion cycles each having an even number of cycles of the clock signal, wherein the serial-to-parallel converter converts the serial data to parallel data at each conversion cycle of the conversion signal. In the preferred embodiment, the conversion signal consists of alternating conversion cycles of 16 and 18 cycles of the clock signal.