Abstract: A method for forming the conductive layer includes: providing a first conductive film and a solution with a conductive material; coating a surface of the first conductive film with the solution, before performing the coating, a temperature of the first conductive film being lower than an evaporation temperature or a sublimation temperature of the solution; and in a process step of performing the coating or after performing the coating, heating the first conductive film, such that the temperature of the first conductive film is higher than or equal to the evaporation temperature or the sublimation temperature of the solution, and forming a second conductive film covering the surface of the first conductive film, wherein the second conductive film including the conductive material.

Abstract: An interconnection structure for metal lines, a method of fabricating the same, and a semiconductor device are provided. A plurality of interconnection structure layers are stacked one above another on a substrate with the support of at least one supporting and covering layer. In each of the interconnection structure layers, spaces between a plurality of conductive components are filled with air which has a low dielectric constant, rather than with dielectric material. Thus, parasitic capacitances in the interconnection structure can be significantly reduced and RC delay can be mitigated.

Abstract: An interconnection structure for metal lines, a method of fabricating the same, and a semiconductor device are provided. A plurality of interconnection structure layers are stacked one above another on a substrate with the support of at least one supporting and covering layer. In each of the interconnection structure layers, spaces between a plurality of conductive components are filled with air which has a low dielectric constant, rather than with dielectric material. Thus, parasitic capacitances in the interconnection structure can be significantly reduced and RC delay can be mitigated.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: A method for decapsulating an integrated circuit package in the absence of a mask is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided and drained. The caustic solution is capable of etching the molding compound while in continuous contact with the molding compound to etch the molding compound. As a consequence, the molding compound is removed so that the circuit element in the package is substantially exposed.

Abstract: A method for repairing a semiconductor structure having a current-leakage issue includes finding a semiconductor structure having a current-leakage issue through application of a test voltage from an electric test device and applying an electric power stress to the semiconductor structure to melt a stringer or a bridge between two conductive elements or to allow the stringer or the bridge to be oxidized.

Abstract: An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same.

Abstract: A bump structure including a base portion, an inlaid wire segment, and a protruding tail segment is provided. The base portion is bonded on a bonding site. The inlaid wire segment is pressed into a top surface of the base portion. The protruding tail segment extends from the inlaid wire segment. The methods for forming the bump structure are also provided.

Abstract: A method for decapsulating an integrated circuit package without the need of using a mask during the decapsulation process is disclosed. First, a package is provided. The package includes at least a circuit element and a molding compound enclosing the circuit. Second, a caustic solution is simultaneously provided. The caustic solution is capable of etching the molding compound and intermittently contacts a pre-selected area of the molding compound to etch the molding compound. As a consequence, the caustic solution removes the molding compound in the pre-selected area so the circuit element in the package is substantially exposed.

Abstract: A method for storing wafers is disclosed. A plurality of wafers are placed into the wafer cassette box. The wafer cassette box is hermetically sealed and pumped down to vacuum for the wafer storage. Alternatively, the wafers carried by a holder conveyed on a wafer conveyor are placed into a pump-down chamber enclosing a section of the wafer conveyor. The pump-down chamber is hermetic sealed and pumped down to vacuum for the wafer storage on the wafer conveyor.

Abstract: A method for obtaining a layout design for an existing integrated circuit, in which, an integrated circuit die is polished with a tilt angle to form an inclined polished surface and one or more images of the inclined polished surface are obtained. The images may be overlapped directly, or the image or the images may be utilized to provide information to obtain a layout design comprising at least one repeating unit structure of the layout structure.

Abstract: A method for forming a semiconductor device comprises providing a substrate. A N type region and a non-N type region are formed in the substrate. The substrate is wet etched to form a protruding portion in the N type region and a concave portion in the non-N type region. A gate structure is formed in the concave portion and insulating spacers are formed on sidewalls of the protruding portion.

Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract: A method for fabricating a cylindrical capacitor is provided. This invention uses a composite structure composed of stacked barrier/scarificing/mask layers to prevent the contact plug of the capacitor from being attacked by wet etchants. An insulating layer is formed over a substrate having a source region, a drain region, and a gate electrode. Then a barrier layer, a sacrificing layer and a mask layer are sequentially formed over the insulating layer. Next, a contact hole is formed over the source region and spacers are formed on the sidewalls of the contact hole. After a storage electrode of the capacitor is formed and exposed portions of the mask layer are removed, the sacrificing layer is isotropically etched using the spacers and the barrier layer as stopping layers. Thereafter, a capacitor dielectric layer and an opposite electrode are formed over the storage electrode thereby completing the capacitor.

Abstract: A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers.