Abstract: A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.

Abstract: A computer readable storage medium includes executable instructions to extract a first language from a first target locale in response to failing to match the target locale to a list of supplied locales, where the list of supplied locales includes all supported locales for which locale-specific data is available. The computer readable storage medium further includes executable instructions to identify a substitute locale within the list of supplied locales based on a total ordering of all supported locales, where the substitute locale includes the first language if the list of supplied locales includes at least one locale within the first language.

Abstract: A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying and conveying a substrate. The first pick-up device is for picking up one of the dies and placing each die on the arranging platform. The second pick-up device is for picking up the dies on the arranging platform and placing the dies on the substrate at the same time.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.

Abstract: A wire-bonding method for a wire-bonding apparatus is provided. The wire-bonding apparatus includes at least a first wire-bonder and a second wire-bonder for respectively bonding at least several first chips in a first region and several second chips in a second region on a substrate simultaneously. The wire-bonding method includes following steps. First, initial position coordinates of the first region and the second region are obtained. Next, it is determined whether a space between the first region and the second region is greater than a predetermined space. When the space between the first region and the second region is greater than the predetermined space, the first wire-bonder and the second wire-bonder respectively bond the first chips and the second chips simultaneously.

Abstract: A die bonder and a die bonding method thereof are provided. The die bonder includes a wafer platform, an arranging platform, a conveyer, at least one first pick-up device and a second pick-up device. The wafer platform is for placing a wafer with several dies. The conveyer is for carrying and conveying a substrate. The first pick-up device is for picking up one of the dies and placing each die on the arranging platform. The second pick-up device is for picking up the dies on the arranging platform and placing the dies on the substrate at the same time.

Abstract: A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on the first substrate. Next, the defected packaging unit is removed from the first substrate to correspondingly form at least one opening in the first substrate. Then, a second substrate including at least one second packaging unit is provided. Later, the second packaging unit is separated from the second substrate. The area of the second packaging unit is less than that of the opening. Subsequently, the second packaging unit is disposed in the opening. The edge of the second packaging unit is placed partially against an inner wall of the opening.

Abstract: A wire-bonding apparatus is used for wire-bonding at least a first chip and a second chip on a substrate at the same time. The wire-bonding apparatus includes at least a first capillary, a second capillary, a driving unit, a processing unit and a database. The driving unit is used for driving the first capillary and the second capillary. The processing unit is used for outputting a command to the driving unit to control the first capillary and the second capillary. The database is used for storing an operating parameter data. The processing unit controls the first capillary and the second capillary according to the operating parameter data.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract: A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, a second titanium layer and a conductive layer. Wherein, the conductive layer is made of aluminum; the first titanium layer and the second titanium layer cover the two surfaces of the conductive layer, respectively. The connectivity between the first titanium layer or the second titanium layer and a macromolecule polymer is stronger than the connectivity between the conductive layer and the macromolecule polymer, so that the peeling or crack caused by poor connectivity between the conductive layer and the adjacent dielectric layers are significantly improved thereby.

Abstract: A semiconductor chip package mainly includes a semiconductor chip, a first dielectric layer disposed on the semiconductor chip, a plurality of conductive traces electrically connected to the semiconductor chip, a second dielectric layer disposed on the conductive traces and the first dielectric layer wherein a portion of the conductive traces are exposed from the second dielectric layer, and a plurality of contacts for external connection formed on the exposed portion of the conductive traces. The semiconductor chip has a surface including an active area, a dummy area surrounding the active area, and a plurality of bonding pads disposed on the active area. The bonding pads are electrically connected to the contacts by the conductive traces. The present invention further provides methods for manufacturing the semiconductor chip package.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: A semiconductor chip with bumps formed therein comprises an active surface, a plurality of bonding pads, a passivation layer, a plurality of first UBMs (under bump metallurgy), a second UBM, a plurality of first bumps, and a plurality of second bumps. The bonding pads are disposed on the active surface of the semiconductor chip. The passivation layer covers the active surface of the semiconductor chip with the pads exposed out of the passivation layer. The first UMBs are individually disposed on the bonding pads. The second UMB is disposed on at least two of the bonding pads. The first bumps are disposed on the first UMBs. The second bumps are disposed on the second UBM.

Abstract: A bump structure on a contact pad and a fabricating process thereof. The bump comprises an under-ball-metallurgy layer, a bonding mass and a welding lump. The under-ball-metallurgy layer is formed over the contact pad and the bonding mass is formed over the under-ball-metallurgy layer by conducting a pressure bonding process. The bonding mass having a thickness between 4 to 10 ?m is made from a material such as copper. The welding lump is formed over the bonding mass such that a sidewall of the bonding mass is also enclosed.