Abstract: An illumination system that provides an illumination beam is provided. The illumination system includes a first light source module, a second light source module, a third light source module, a first optical element, a second optical element, and a third optical element. The first light source module and the second light source module provide a first color light beam, a second color light beam, and a third color light beam. The third light source module provides a third color light beam. The first optical element, the second optical element and the third optical element are disposed on transmission paths of the first color light beam, the second color light beam and the third color light beam, and the first light source module and the second light source module are respectively located on opposite sides of the first optical element and the second optical element.

Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.

Abstract: A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating. layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.

Abstract: A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.

Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.

Abstract: A gate driver with reduced voltage fluctuations driving a display device generates pulse signals shifted in a specified phase. The gate driver includes connected unit circuits. Each unit circuit includes an output terminal, input and output transistors, and a holding module. First and second control signals, alternating oppositely between high and low states, govern the two transistors. The input transistor is controlled by a first control signal and outputs a high level voltage to a first node based on a trigger signal. The output transistor outputs the shifted pulse signal synchronously with a clock control signal, based on the high level voltage of the first node. Initially, the trigger signal is low and the first and second control signals are high. The holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.

Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.

Abstract: A gate driver with reduced voltage fluctuations driving a display device generates pulse signals shifted in a specified phase. The gate driver includes connected unit circuits. Each unit circuit includes an output terminal, input and output transistors, and a holding module. First and second control signals, alternating oppositely between high and low states, govern the two transistors. The input transistor is controlled by a first control signal and outputs a high level voltage to a first node based on a trigger signal. The output transistor outputs the shifted pulse signal synchronously with a clock control signal, based on the high level voltage of the first node. Initially, the trigger signal is low and the first and second control signals are high. The holding module outputs the low level voltage to the output terminal based on the first control signal and the second control signal.

Abstract: A gate driving circuit which allows narrower framing of a display screen includes cascade-connected gate driving modules. Each gate driving module is electrically coupled to first and second scan lines and outputs scanning signals to the first and the second scan lines in a time-division manner in response to first and second clock signals. Each gate driving module includes an input transistor, and first and second output transistors. The input transistor receives a trigger signal for activating the gate driving module. The input transistor controls the first output transistor to output first scanning signal to first scan line in response to the first clock signal and controls the second output transistor to output second scanning signal to the second scan line in response to the second clock signal.

Abstract: A display device comprising thin film transistor array substrate includes scan lines, data lines, pixel units, and a source driver. Each pair of scan lines extends in a first direction and data lines extend in a second intersecting direction. Of the first and second sub-pixels in each pixel unit, the first sub-pixel connects to the first scan line, and the second sub-pixel connects to the second scan line. The first and second sub-pixels also straddle and connect to one data line. Source driver supplies the data lines with voltages and the voltage to the first sub-pixel is greater than the voltage to the second sub-pixel. This configuration avoids appearance of stripes on the display arising from charging rates of adjacent pixel columns not being the same. A display panel using the thin film transistor array substrate is also provided.

Abstract: A thin film transistor array substrate with always-equal parasitic capacitances for a display includes scan lines, data lines, common lines, and pixel units. First and second scan lines extend in a first direction. Data and common lines extend in a second intersecting direction and are arranged to alternate in the first direction. First and second sub-pixels of pixel units are distributed on either side of and connected to one of a scan line pair. The first and second sub-pixels also straddle and connect to one data line. Bridges on a common line cover a portion of one scan line pair in the second direction and each bridge overlaps first and second scan lines. First scan line overlap with bridge is equal to second scan line overlap. A display panel using the thin film transistor array substrate is also provided.

Abstract: A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.

Abstract: A display device includes a display area and a peripheral area surrounding the display area. The display device includes a thin film transistor substrate, a plurality of thin film transistors, a first common line, and a storage capacitor line. The first common line, the storage capacitor, and a gate electrode of the thin film transistor are located in a same layer. The first common line is directly electrically coupled to the storage capacitor line.

Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.

Abstract: A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.

Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.

Abstract: An array substrate includes a display area, an edge area, data lines, pixel units, a feedback transmission line, a feedback control circuit, and a display drive circuit. The edge area surrounds the display area. The feedback transmission line, the feedback control circuit, and the display drive circuit are spatially corresponding to the edge area. The feedback transmission line electrically connects at least one of the data lines and the feedback control circuit. The feedback transmission line detects a data signal transmitted by the data lines and outputs a feedback signal to the feedback control circuit. The feedback control circuit outputs a common voltage to the display drive circuit according to the feedback signal. The display drive circuit outputs the common voltage to the pixel units.

Abstract: A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.

Abstract: An active array matrix substrate of a display panel includes a number of scan lines parallel to each other and arranged in a first metal layer of a first substrate, a number of data lines parallel to each other and arranged in a second metal layer of the first substrate, a number of gate electrodes arranged in the first metal layer, a number of source electrodes arranged in the second metal layer, and a number of drain electrodes arranged in the second metal layer. The source electrode includes at least one source extending portion spaced from and configured to overlap with the first metal layer. The drain electrode includes at least one drain extending portion spaced from and configured to overlap with the first metal layer.

Abstract: A display panel includes a substrate, a plurality of thin film transistors (TFTs), a plurality common electrodes, a plurality of common electrode lines, a plurality of coupling electrodes, and a plurality of pixel electrodes. Each of the TFTs comprises a gate, a source, a drain and a channel layer coupling the source to the drain. The gate, the common electrodes, and the common electrode lines are formed on a surface of the substrate and are separated from each other. Each of the coupling electrodes couples a corresponding common electrode to a corresponding common electrode line, and a space is defined between the corresponding common electrode and the corresponding common electrode line.