Abstract: A semiconductor device with dummy patterns for alleviating micro-loading effect includes a semiconductor substrate having thereon a middle annular region between an inner region and an outer region; a SiGe device on the semiconductor substrate within the inner region; and a plurality of dummy patterns provided on the semiconductor substrate within the middle annular region. At least one of the dummy patterns contains SiGe.

Abstract: A capacitor structure is provided. The capacitor structure includes a plurality of first conductive lines paralleled disposed in a conductive layer on a substrate, wherein the first conductive lines are isolated to each other in the conductive layer and are grouped into a first electrode group and a second electrode group, an insulating layer formed on the first conductive lines and in the space between the first conductive lines, a second conductive line formed on the insulating layer electrically connected to the first conductive lines of the first electrode group, and a third conductive line formed on the insulating layer electrically connected to the first conductive lines of the second electrode group.

Abstract: An interconnection structure includes an inter-layer dielectric; a topmost copper metal layer inlaid into the inter-layer dielectric; an insulating layer disposed on the inter-layer dielectric and the topmost copper metal layer; a via opening in the insulating layer for exposing a top surface of the topmost copper metal layer, wherein the via opening consists of an inwardly tapered upper via portion and a lower via portion having a substantially vertical sidewall profile; and an aluminum layer filling into the via opening.

Abstract: An integrated inductor has a winding. The winding includes a first level metal layer inlaid in a first dielectric layer, a second level metal layer inlaid in a second dielectric layer above the first dielectric layer, and a first line-shaped via structure inlaid in a slot of a third dielectric layer interposed between the first and second dielectric layers for interconnecting the first and second level metal layers.

Abstract: A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.

Abstract: A memory structure, a memory device and a manufacturing method thereof are provided. First, a substrate is provided and a dielectric layer is formed over the substrate. Then, a pattern is formed in the dielectric layer. An amorphous silicon layer is formed in the pattern and over the dielectric layer. The amorphous silicon layer is patterned to form an electrode over the pattern. Then, a spacer is formed on the sidewall of the electrode. A selective hemispherical grains (HSGS) layer is formed over the surface of the electrode and the surface of the spacer.

Abstract: A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. Afterward, a composite dielectric layer is formed on the substrate and covers the conductive lines. Finally, a plurality of word lines are formed on the composite dielectric layer.

Abstract: A method of manufacturing a split-gate flash memory device is disclosed. On a semiconductor substrate having a plurality of parallel conductive lines, a plurality of doped regions are formed by an ion implantation using the conductive lines as mask. Then, the conductive lines are trimmed for thinning the cover area. Afterward, a composite dielectric layer is formed on the substrate and covers the conductive lines. Finally, a plurality of word lines are formed on the composite dielectric layer.

Abstract: The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first mask layer is oxidized into a protective oxide layer during thermal oxidation for forming a liner oxide layer. The protective oxide layer can protect the top corner of a trench from he formation of pits during subsequent etching for removing a pad oxide layer, thereby preventing a kink effect. Furthermore, after forming the liner oxide layer and before filling the trench with an insulting layer, a buffer layer formed over a substrate not only prevents the sidewalls of the trench from oxidizing, but also prevents a lateral etching damage during subsequent etching for removing the pad oxide layer.

Abstract: A layer of metal is deposited on the surface of a layer of dielectric material and layer of protective material such as a thin layer of silicon oxide is provided on the layer of metal. An etch mask, which might be photoresist, is provided on the layer of protective material. The protective layer is etched through and the metal layer is etched using the photoresist etch mask. Little or no overetching is performed at this time, so it is likely that stringers from the metal layer will be left between the patterned wiring lines. Sidewall structures are then formed alongside the metal lines to protect the sidewalls of the wiring lines from undercutting and corrosion in subsequent etching steps. Overetching is then performed to remove any metal stringers, with the protective layer and the sidewall structures acting as masks for the overetching process, protecting the wiring lines from thinning during this etch process.

Abstract: A process is disclosed for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout. The buried diffusion is free from being inadvertently cut apart to cause open-circuiting. A bird's beak oxide layer is formed protecting the buried diffusion junction region from undesirable etching, thereby preventing from damaging consumption by etching. The buried diffusion junctions formed may serve as the source/drain region for the transistor.

Abstract: A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.

Abstract: Dielectric structures of the type that might be used in DRAMs, other memory devices, and integrated thin film transistors include repeated silicon oxide/silicon nitride layers. For example, the dielectric structure may have a silicon oxide/silicon nitride/silicon oxide/silicon nitride/silicon oxide or "ONONO" layer structure. Such repeated layer structures exhibit higher levels of breakdown voltage than more conventional "ONO" structures. Most of the growth of the five layer ONONO or more complicated dielectric structure can be accomplished in a single furnace through a series of temperature steps performed under different gas ambients. A substrate having a polysilicon lower electrode is introduced to a furnace and a lowest layer of silicon oxide is grown on the polysilicon electrode in an ammonia ambient. A first silicon nitride layer is grown in NH.sub.3 and SiH.sub.2 Cl.sub.

Abstract: A method of designing an active layer mask with a dummy pattern by computer aided design (CAD) in shallow trench isolation using chemical mechanical polishing (CMP) to achieve global planarization. In this method, an original mask is provided with an active region including a diffusion area pattern, a polysilicon area pattern and a well area pattern. The diffusion area pattern and the polysilicon area pattern are expanded by an area of dimension a and the well area pattern is extended inward and outward to an area of dimension b. The expanded diffusion, polysilicon and well areas form a first pattern area. The first pattern area is subtracted from the whole region to obtain a second pattern area. A third pattern area is obtained by performing an AND operation on a dummy array pattern and the second pattern area. Expanding the third pattern area to an area of dimension c, a fourth pattern area is obtained.

Abstract: A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

Abstract: A method of automatically generating dummy metals for multilevel interconnection makes use of a quantum array pattern accompanying an operating pattern to from a metal pattern. The method comprises the combination selected from intersection (AND), union (OR), oversizing, downsizing, or incorporation operation through computer-aided design (CAD). Therefore, the application of the metal pattern to a process for fabricating a multimetal structure can acquire full planarization between two metal layers because of the arrangement that several dummy metals are positioned among the metal lines to diminish the spacing which exceeds the planarization limit. Also, the dummy metals are shaped in blocks thereby preventing the loading effect during etching and decreasing the parasitic capacitance therebetween.

Abstract: The pull down transistor of a static SRAM semiconductor device is formed with oxide and polysilicon regions formed on a doped silicon substrate. A masking area is formed over the drain side of the polysilicon and the areas of the drain region proximal to the gate in the silicon and oxide layers below. N+ dopant is implanted into the unmasked areas of said substrate about the polysilicon region with the drain doping offset by the resist overlying the proximal portion of the drain region. A spacer is formed by chemical vapor deposition about the polysilicon region. Next an N- implantation follows with the offset provided by the spacers about the polysilicon region.

Abstract: A method for fabricating a capacitor having a fin-shaped electrode on a dynamic random access memory (DRAM) cell having increased capacitance was achieved. The capacitor is fabricated on a silicon substrate having an active device region. The device region contains a metal-oxide-semiconductor field effect transistor (MOSFET), having one capacitor aligned over and contacting the source/drain of the MOSFET in the device region. The capacitor is increased in capacitance by forming a multilayer insulator structure over the storage capacitor area and recessing alternate layers, then using the form as a mold for forming a polysilicon fin-like bottom capacitor electrode. The remaining multilayer mold is removed and a high dielectric constant insulator is deposited on the bottom electrode as the inter-electrode dielectric.

Abstract: In accordance with this invention, a method of manufacture of a semiconductor memory device comprises the following steps: forming field oxide structures on a semiconductor substrate, forming a gate oxide layer on exposed surfaces of the substrate, forming a first word line layer on the device, patterning the first word line layer by forming a first patterned mask mask with a first set of openings therein and etching the first word line layer through the openings in the first mask to form conductor lines, forming a first dielectric layer on the surface of the first word line layer on the device, forming a second word line layer on the first dielectric layer, patterning the second word line layer by forming a second patterned mask with a second set of openings therein and etching portions of the second word line layer therethrough, h) forming a second dielectric layer on the surface of the second word line layer on the device, and implanting ions of dopant into predetermined locations into the semiconductor su

Abstract: The invention describes the fabrication and use of a sub-resolution phase shift mask. The mask is formed using a single alignment step with all other alignment steps being accomplished by self alignment. This self alignment is made possible by using vertical anisotropic etching of an opaque material layer to form opaque spacers at the pattern edges of phase shifting material. The opaque spacers combine with phase shifting and other opaque regions of the mask to provide improved image resolution and depth of focus tolerance at the surface of an integrated circuit wafer.