Patents by Inventor Ming-Wei Huang

Ming-Wei Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240174512
    Abstract: A MEMS probe and manufacturing method thereof are provided. The method is mainly to form connected first-level, second-level, and third-level pin grooves on both sides of the silicon substrate through an etching process, followed by two electroplating processes to deposit nickel-cobalt-phosphorus alloy in the first-level pin groove to form the tip of the microprobe, and to deposit nickel-cobalt alloy in the second-level pin groove and the third-level pin to form the pin head and pin arm, thereby forming a three-level microprobe. A circuit substrate made of ceramic material is disposed with at least one window, the surface of the circuit substrate adjacent to the window is provided with a plurality of circuit pads, and the circuit substrate is abutted to the pin arm of the microprobe. The silicon substrate is then removed, to form a plurality of cantilever microprobes made of nickel-cobalt-phosphorus alloy and nickel-cobalt alloy on the circuit substrate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: SHANG-KUANG WU, YU-TSUNG FU, MING-WEI HUANG
  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11996466
    Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Huang Huang, Ming-Jhe Sie, Cheng-Chung Chang, Shao-Hua Hsu, Shu-Uei Jang, An Chyi Wei, Shiang-Bau Wang, Ryan Chia-Jen Chen
  • Publication number: 20240170381
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Application
    Filed: February 1, 2024
    Publication date: May 23, 2024
    Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
  • Publication number: 20240163904
    Abstract: Methods, systems, and apparatuses are provided for sidelink resource selection or exclusion of multi-consecutive slot transmission (MCSt) in a wireless communication system to enhance and/or modify Legacy sidelink Mode 2 operation for the MCSt. A method of a first device can comprise triggering or requesting sensing-based resource selection or re-selection for performing one or more Physical Sidelink Shared Channel (PSSCH) or Physical Sidelink Control Channel (PSCCH) transmissions in a sidelink resource pool in unlicensed or shared spectrum, determining a first parameter for determining or initializing candidate multi-slot resources, receiving a Sidelink Control Information (SCI) for reserving one or more sidelink resources, selecting a number of sidelink resources from valid/identified/remaining candidate multi-slot resources after exclusion, and performing the one or more PSSCH or PSCCH transmissions on at least one of the selected number of sidelink resources.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 16, 2024
    Inventors: Chun-Wei Huang, Ming-Che Li, Yi-Hsuan Kung, Li-Chih Tseng
  • Publication number: 20240163920
    Abstract: Methods, systems, and apparatuses are provided for sidelink transmission in a wireless communication system. In various embodiments, with this and other concepts, systems, and methods of the present invention, a method for a first User Equipment (UE) comprises receiving configuration for configuring two starting symbols in a Transmission Time Interval (TTI) in a sidelink resource pool, wherein a second starting symbol of the two starting symbols is later than a first starting symbol of the two starting symbols, transmitting a signaling to a second UE, wherein the signaling comprises or indicates information of a first specific (symbol) location of Sidelink (SL) Channel State Information Reference Signal (CSI-RS), and performing sidelink transmission with SL CSI-RS in the TTI to the second UE.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 16, 2024
    Inventors: Chun-Wei Huang, Ming-Che Li
  • Publication number: 20240162038
    Abstract: A photomask structure including a first layout pattern and a second layout pattern is provided. The second layout pattern is located on one side of the first layout pattern. The first layout pattern and the second layout pattern are separated from each other. The first layout pattern has a first edge and a second edge opposite to each other. The second layout pattern has a third edge and a fourth edge opposite to each other. The third edge of the second layout pattern is adjacent to the first edge of the first layout pattern. The second layout pattern includes a first extension portion exceeding an end of the first layout pattern. The first extension portion includes a first protruding portion protruding from the third edge of the second layout pattern. The first protruding portion exceeds the first edge of the first layout pattern.
    Type: Application
    Filed: February 10, 2023
    Publication date: May 16, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Chien Heng Liu, Chia-Wei Huang, Yung-Feng Cheng, Ming-Jui Chen
  • Publication number: 20240153896
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11961919
    Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Chang, Hsiu-Hao Tsao, Ming-Jhe Sie, Shun-Hui Yang, Chen-Huang Huang, An Chyi Wei, Ryan Chia-Jen Chen
  • Publication number: 20240121804
    Abstract: Methods, systems, and apparatuses can comprise a first device in a wireless communication system receiving configuration of one or more first sidelink resource pools for at least sidelink data transmission and configuration of one or more second sidelink resource pools for sidelink reference signal transmission, receiving a Downlink Control Information (DCI) for sidelink, wherein the DCI comprises a resource pool index corresponding to one sidelink resource pool, determining the DCI for scheduling sidelink data transmission or sidelink reference signal transmission based on at least the resource pool index or the one sidelink resource pool, acquiring or determining fields or information in the DCI based on the determination that the DCI is for scheduling sidelink data transmission or sidelink reference signal transmission, determining a sidelink resource based on the acquired or determined fields, or the information in the DCI, and performing a sidelink transmission on the sidelink resource in the one sidelin
    Type: Application
    Filed: September 27, 2023
    Publication date: April 11, 2024
    Inventors: Ming-Che Li, Chun-Wei Huang, Li-Chih Tseng
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11934213
    Abstract: A liquid-cooling device includes multiple water blocks and at least one connection tube. Each of the water blocks has a water incoming end, a water outgoing end and a water-receiving space in communication with the water incoming end and the water outgoing end. The connection tube is disposed between each two water blocks. Two ends of the connection tube are respectively connected with the water incoming end of one of the two water blocks and the water outgoing end of the other water block, whereby the water-receiving spaces of the two water blocks communicate with each other via the connection tube. The connection tube has at least one bellows section between two ends of the connection tube. The liquid-cooling device solves the problems of the conventional liquid-cooling device that when the water block is welded, thermal deformation is produced to cause tolerance and the manufacturing cost is higher.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: March 19, 2024
    Assignee: ASIA VITAL COMPONENTS (CHINA) CO., LTD.
    Inventors: Pai-Ling Kao, Sung-Wei Lee, Kuan-Lin Huang, Ming-Tsung Yang
  • Patent number: 11937334
    Abstract: Methods, systems, and apparatuses for Sidelink Discontinuous Reception (SL DRX) in a wireless communication system to avoid ambiguity on slot offset calculations on SL DRX. A method for a UE comprises performing a SL communication associated with a destination Identity (ID), having a SL DRX configuration associated with the SL communication, wherein the SL DRX configuration comprises at least an on-duration timer and a DRX cycle, deriving a first offset associated with the SL communication based on the destination ID and the DRX cycle, deriving a second offset associated with the SL communication based on the destination ID and a number of slots per subframe, starting the on-duration timer after a time period determined based on the second offset from the beginning of a subframe, wherein the subframe is determined based on at least the first offset, and monitoring Sidelink Control Information (SCI) when the on-duration timer is running.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: March 19, 2024
    Assignee: ASUSTek Computer Inc.
    Inventors: Yi-Hsuan Kung, Li-Chih Tseng, Chun-Wei Huang, Ming-Che Li
  • Patent number: 11929314
    Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 11924876
    Abstract: Methods and apparatuses for handling partial sensing and discontinuous reception for sidelink communication to reduce potential latency due to additional sensing and to improve resource utilization efficiency. Various embodiments can comprise a first device performing sidelink communication to at least a second device, or a second device in a sidelink resource pool, and triggering to perform resource selection for a sidelink data at a timing, wherein the first device (already) receives or monitors sidelink control information for a (contiguous) time duration before the timing. The first device can perform sensing for a contiguous sensing duration after the timing, determine or select a first sidelink resource from a set of sidelink resources, and perform a first sidelink transmission on the first sidelink resource for transmitting the sidelink data to the second device.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 5, 2024
    Assignee: ASUSTek Computer Inc.
    Inventors: Ming-Che Li, Chun-Wei Huang, Li-Chih Tseng
  • Patent number: 10821332
    Abstract: A method for manufacturing a golf club head having a weight member includes: providing a weight block made of a metal material; disposing an isolation layer on the weight block to form the weight member; delivering a wax material to form a wax pattern covering a portion of the weight member; coating the weight member and the wax pattern with a shell mold plaster to form a shell mold covering the same; performing a de-waxing process which leaves a mold cavity in the shell mold; and casting a molten metal material in the mold cavity to form a club head main body, and removing the shell mold to form the golf club head having the weight member embedded in the club head main body. A golf club head manufactured by the method is also disclosed.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 3, 2020
    Assignee: ADVANCED INTERNATIONAL MULTITECH CO., LTD.
    Inventors: Min-Tsung Chen, Shang-Ju Tsai, Ming-Fu Su, Kun-Han Lu, Ming-Wei Huang, Chun-Hao Huang
  • Patent number: 8164603
    Abstract: A method of measuring image-sticking of a display is described. A display having N gray levels is provided. Next, an image-stick test frame having at least a first pattern having a low gray level and at least a second pattern having a high gray level is displayed on the display. After the image-stick test frame is displayed for a while, an image-stick region and a non-image-stick region are formed on the display. A measuring frame is then displayed on the display, wherein the non-image-stick region in the measuring frame has a standard gray level M. A plurality of middle gray levels is sequentially displayed on the image-stick region in the measuring frame. When the boundary between the non-image-stick region and the image-stick region in measuring frame is the lightest, the middle gray level is converted into an image-sticking level.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: April 24, 2012
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Chien-Pang Lee, Chien-Hui Yang, Ming-Wei Huang, Mei-Chi Fu, Pai-Chung Chien
  • Patent number: 7932891
    Abstract: A multiple scan method for driving a display and a display therewith is provided. The multiple scan method is achieved by alternately driving the active pixels in the display twice or more times for expediting response time of these active pixels to reach the target luminance in the display. The pixels in the display are charged or discharged twice or more times within one frame period. By such design, the response time is shortened and quality for showing motion pictures is significantly improved.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: April 26, 2011
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventors: Ming-Wei Huang, Wen-Tse Tseng, Mu-Shan Liao, Juin-Ying Huang
  • Publication number: 20110068832
    Abstract: A driving circuit for a power MOSFET includes a first switch, a second switch, a third switch and a fourth switch. The first switch is connected to a first node, a second node and a first power end. The first power end supplies a first voltage. The second switch is connected to the first node, the second node and a first ground end. The third switch is connected to the second node, a third node and the first power end. The fourth switch is connected to the second node, the third node and a second ground end. The power MOSFET is connected to the third node and a PWM signal is inputted into the first node. The PWM signal has a second voltage lower than the first voltage.
    Type: Application
    Filed: October 29, 2009
    Publication date: March 24, 2011
    Inventors: Ying-Pei Chen, Ming-Wei Huang