Abstract: A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of pixel structures, a plurality of second signal lines, a plurality of light sensing units, a plurality of third signal lines, and a plurality of touch units is provided. The first signal lines are arranged on the substrate along a first direction. The pixel structures are disposed between the first signal lines. The second signal lines are arranged on the substrate along the first direction. The light sensing units are disposed between the second signal lines. Any adjacent two of the light sensing units are electrically connected to one of the second signal lines and are symmetrically disposed with respect to the second signal line. The third signal lines and the second signal lines are alternately arranged on the substrate. The touch units are electrically connected to the third signal lines.

Abstract: A pixel array substrate including a substrate, a plurality of display pixels, a plurality of sensing pixels, and a read-out circuit is provided. The substrate includes a first region and a second region. The second region is located between the first region and an edge of the substrate. The display pixels are disposed on the first region and the second region of the substrate. The sensing pixels are disposed on the first region of the substrate. The read-out circuit is electrically connected to the sensing pixels. A portion of the read-out circuit is disposed on the second region of the substrate and the portion of the read-out circuit is located between two display pixels of the display pixels.

Abstract: A display apparatus includes a first substrate, a plurality of pixel structures disposed on the first substrate, a light sensor disposed on the first substrate, an insulation layer disposed on the light sensor, a first light shielding pattern, a second substrate disposed opposite to the first substrate, a second light shielding pattern, and a display medium. Each pixel structure includes an active device and a pixel electrode electrically connected to the active device. The first light shielding pattern is disposed on the insulation layer and located above the light sensor. The second light shielding pattern is disposed on the second substrate and has an opening. The opening of the second light shielding pattern and the first light shielding pattern define at least one slit, and the at least one slit and the light sensor are partially overlapped. The display medium is disposed between the first substrate and the second substrate.

Abstract: A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.

Abstract: A pixel array substrate including a substrate, an active device, a planarization layer, a first conductive layer, a first insulation layer and a second conductive layer is provided. The active device is disposed on the substrate. The planarization layer covers the active device and has a first opening. The first conductive layer is disposed on the planarization layer and is electrically connected with a first end of the active device. The first insulation layer is disposed on the first conductive layer. The second conductive layer is disposed on the first insulation layer. The first conductive layer and the second conductive layer cover a side surface of the first opening of the planarization layer.

Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.

Abstract: A display panel includes a substrate, at least one first transistor, and at least one second transistor. The substrate includes at least one reflective region and at least one transmissible region. The first transistor is configured on the substrate and located on the corresponding reflective region. Each of the first transistors includes a first active layer. The second transistor is configured on the substrate and located on the corresponding transmissible region. Each of the second transistors includes a second active layer. A material of the first active layer is different from a material of the second active layer.

Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.

Abstract: An array substrate includes a substrate and a plurality of pixel structures. At least one pixel structure includes a gate electrode, a gate insulating layer, a source electrode and a drain electrode, a patterned semiconductor layer, a first passivation layer, and a transparent conductive pattern disposed in a pixel region of the substrate. The patterned semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The first semiconductor pattern substantially corresponds to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode. The second semiconductor pattern covers a portion of the drain electrode. The first passivation layer is disposed on the patterned semiconductor layer and has a first opening exposing a portion of the second semiconductor pattern. The transparent conductive pattern is disposed on the first passivation layer and electrically connected to the second semiconductor pattern through the first opening.

Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Abstract: A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Abstract: A (liquid crystal display) LCD includes a pixel array and a gate driving circuit. The pixel array includes a plurality of first oxide thin film transistors, a first oxide thin film transistor of the first oxide thin film transistors with a shortest channel length having a first channel length. The gate driving circuit is coupled to the pixel array for driving the pixel array, and includes a plurality of second oxide thin film transistors. The second oxide thin film of the second oxide thin film transistors with a longest channel length has a second channel length. A ratio of the second channel length and the first channel length is greater than 1.5. By limiting the ratio of the second channel length and the first channel length, the aperture ratio of the display panel can be improved without deteriorating the operation stability of the LCD.

Abstract: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring.

Abstract: A core-shell structure with magnetic, thermal, and optical characteristics. The optical absorption band is tailorable by choice of the mixing ratio of the core/shell component to give the desired shell thickness. The core-shell structure is particularly suitable for biomedical applications such as MRI (magnetic resonance imaging) developer, specific tissue identification developer, and magnetic thermal therapy.

Abstract: A semiconductor chip having through silicon vias (TSV) and a stacked assembly including the chip are revealed. The chip has a plurality of first and second bonding pads disposed on two opposing surfaces of a semiconductor substrate respectively. Through hole vertically penetrate through the semiconductor substrate and the first and second bonding pads. By forming first extruded ring, the first bonding pad has a first contact surface located between the first extruded ring and the through hole. By forming second extruded ring, the second bonding pad has a second contact surface located outside and adjacent to the second extruded rings to encircle the second extruded ring. The second extruded ring has a proper dimension to fit in the first extruded ring.

Abstract: A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. The second bump is disposed on the substrate. The height of the second bump is greater than that of the first bump. The elastic bump of the present invention can be used for measuring the bonding process quality.

Abstract: A bump structure on a substrate including at least one first electrode, at least one first bump, at least one second bump is provided. The first electrode is disposed on the substrate. The first bump is disposed on the first electrode. The second bump is disposed on the substrate. The height of the second bump is greater than that of the first bump. The elastic bump of the present invention can be used for measuring the bonding process quality.

Abstract: Magnetic nanoparticles with fluorescent properties and specific targeting functions. The fluorescent magnetic nanoparticle includes a magnetic nanoparticle, a biocompatible polymer chemically modifying the magnetic nanoparticle, a fluorescent dye coupled to the biocompatible polymer, and a specific targeting agent coupled to the biocompatible polymer. The fluorescent and magnetic properties of the nanoparticles provide different types of signal sources and therefore, prompt imaging using different types of imaging techniques to reconfirm foci is feasible.

Abstract: A core-shell structure with magnetic, thermal, and optical characteristics. The optical absorption band is tailorable by choice of the mixing ratio of the core/shell component to give the desired shell thickness. The core-shell structure is particularly suitable for biomedical applications such as MRI (magnetic resonance imaging) developer, specific tissue identification developer, and magnetic thermal therapy.

Abstract: A method for forming a superparamagnetic nanoparticle. The method includes providing an aqueous solution comprising Fe2+ and Fe3+ ions and adding alkali to the aqueous solution. An iron oxide nanoparticle is formed by subjecting the aqueous solution to ultrasonic vibration and collected.