Patents by Inventor Ming-Yi Huang

Ming-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240178102
    Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.
    Type: Application
    Filed: April 21, 2023
    Publication date: May 30, 2024
    Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11994970
    Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 28, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
  • Patent number: 11996227
    Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
  • Publication number: 20240158677
    Abstract: An adhesive and a method for removing the adhesive are provided. The adhesive includes component (A) and component (B). Component (A) is a combination of a first acrylate resin and a first compound, a second acrylate resin, a combination of the first acrylate resin and the second acrylate resin, a combination of the second acrylate resin and the first compound, or a combination of the first acrylate resin, the second acrylate resin and the first compound. The first acrylate resin has an iodine value from 0 to 3. The second acrylate resin has an acrylate group, or methacrylate group. Component (B) is a near infrared sensitizer. The first compound has at least two reactive functional groups, wherein the reactive functional groups are acrylate group, methacrylate group, or a combination thereof.
    Type: Application
    Filed: June 16, 2023
    Publication date: May 16, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shuang-Huei CHEN, Yao-Jheng HUANG, Te-Yi CHANG, Ming-Tzung WU
  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Patent number: 11971062
    Abstract: A mounting system is disclosed that includes a bracket configured to mount an object on a structure. The bracket includes a front panel, two side panels extending from the front panel, and a plurality of slots. Each slot is configured to accept a projection connected to the object and retain the projection within the slot. The bracket further includes a plurality of apertures. The mounting system further includes a retainer configured to extend into the bracket through the plurality of apertures and prevent, at least in part, the plurality of projections, retained by the bracket in the plurality of slots, from being withdrawn from the plurality of slots.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: April 30, 2024
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Ming-Lung Wang, Hong-Yi Huang
  • Publication number: 20240115681
    Abstract: Provided is a pharmaceutical composition including an active pharmaceutical ingredient, a toll-like receptor (TLR) agonist, a stimulator of interferon genes (STING) agonist, and a pharmaceutically acceptable carrier. Also provided are a method for inducing immune response and a method for treating or preventing cancer or an infectious disease, including administering an effective amount of the pharmaceutical composition to a subject in need thereof.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 11, 2024
    Applicant: National Health Research Institutes
    Inventors: Tsung-Hsien Chuang, Jing-Xing Yang, Jen-Chih Tseng, Zaida Nur Imana, Ming-Hsi Huang, Guann-Yi Yu
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11935871
    Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
  • Publication number: 20240081081
    Abstract: A ferroelectric memory device and a semiconductor die are provided. The ferroelectric memory device includes a gate electrode; a channel layer, overlapped with the gate electrode; source/drain contacts, in contact with separate ends of the channel layer; a ferroelectric layer, lying between the gate electrode and the channel layer; and a first insertion layer, extending in between the ferroelectric layer and the channel layer, and comprising a metal carbonitride or a metal nitride.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Lee, Chung-Te Lin, Han-Ting Tsai, Wei-Gang Chiu, Yen-Chieh Huang, Ming-Yi Yang
  • Patent number: 11924534
    Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 5, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Jyun-Jia Cheng, Yu Chen Lai, Ming-Ta Chou, Cheng-Feng Lin, Chen-Yi Huang
  • Patent number: 11571841
    Abstract: A plastic molded product includes a plastic body provided with a plurality of holes, which are recessed in a common depth direction, on a surface of the plastic body. The holes include: an inner surface including an inlet a specific reference plane perpendicular to the depth direction and including at least a portion of the inlet and a depth reference point, which is spaced away from a center point on an inlet side of the specific reference plane toward a bottom side of the hole, the depth reference point being spaced away by a distance equal to ¼ of a maximum value of an inlet side bore diameter on the specific reference plane. A deepmost portion of the inner surface of the hole is in a position which coincides with the reference point or is deeper than the reference point toward the bottom side.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 7, 2023
    Assignee: YKK Corporation
    Inventors: Kenichi Yoshie, Ming Yi Huang, Makoto Ueda
  • Publication number: 20220350384
    Abstract: A method for detecting heat dissipation is provided, including the following steps: sensing a core temperature of a heat emitting component of an electronic device; sensing current power of the heat emitting component when the core temperature is greater than or equal to a warning temperature; and transmitting an assembling check prompt and activating a thermal control circuit (TCC) when the current power is less than thermal design power (TDP) of the heat emitting component. An electronic device is further provided, to execute the method for detecting heat dissipation.
    Type: Application
    Filed: April 21, 2022
    Publication date: November 3, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Kun-Hsin Chiang, Yu-Chieh Chang, Tang-Hui Liao, Wei-Hsian Chang, Wen-Yen Hsieh, Chih-Wei Kuo, Ming-Yi Huang, Ching-Chan Chu, Shun-Po Chang
  • Publication number: 20210216429
    Abstract: A diagnostic system applied to an electronic equipment with a plurality of hardware devices is provided. The hardware devices include a display and a processor, the diagnostic system is executed by the processor to diagnose the hardware devices. The diagnostic system includes a diagnostic test interface, which is displayed on the display and includes a plurality of hardware items corresponding to the hardware devices. Each of the hardware items links to the hardware devices. When at least one of the hardware items is triggered, the processor executes the diagnostic item of the hardware device corresponding to the triggered hardware item.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 15, 2021
    Inventors: Kun-Hsin Chiang, Hsin-Hui Huang, Wei-Hsian Chang, Wen-Yen Hsieh, Ming-Yi Huang, Yu-Chieh Chang, Tang-Hui Liao, Chih-Wei Kuo
  • Publication number: 20200164549
    Abstract: A plastic molded product includes a plastic body provided with a plurality of holes, which are recessed in a common depth direction, on a surface of the plastic body. The holes include: an inner surface including an inlet a specific reference plane perpendicular to the depth direction and including at least a portion of the inlet and a depth reference point, which is spaced away from a center point on an inlet side of the specific reference plane toward a bottom side of the hole, the depth reference point being spaced away by a distance equal to ¼ of a maximum value of an inlet side bore diameter on the specific reference plane. A deepmost portion of the inner surface of the hole is in a position which coincides with the reference point or is deeper than the reference point toward the bottom side.
    Type: Application
    Filed: May 8, 2017
    Publication date: May 28, 2020
    Inventors: Kenichi Yoshie, Ming Yi Huang, Makoto Ueda
  • Patent number: 9455786
    Abstract: An optical transceiver includes a positioning element, a fiber connecting segment, a base and a housing. The positioning element has a first positioning part. The fiber connecting segment tightly fits to the positioning element. The housing supports at least one optical transceiving element and is connected to the positioning element. The base has a second positioning part and is configured for supporting the positioning element and the fiber connecting segment. The first positioning part and the second positioning part define the position of the fiber connecting segment.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 27, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Hsien Liao, Ming-Yi Huang, Te-Hsuan Yang
  • Publication number: 20150349893
    Abstract: An optical transceiver includes a positioning element, a fiber connecting segment, a base and a housing. The positioning element has a first positioning part. The fiber connecting segment tightly fits to the positioning element. The housing supports at least one optical transceiving element and is connected to the positioning element. The base has a second positioning part and is configured for supporting the positioning element and the fiber connecting segment. The first positioning part and the second positioning part define the position of the fiber connecting segment.
    Type: Application
    Filed: July 30, 2014
    Publication date: December 3, 2015
    Inventors: Yu-Hsien LIAO, Ming-Yi HUANG, Te-Hsuan YANG
  • Patent number: 9195017
    Abstract: An optical module includes a first light-guide element, an optical element, a first optical fiber, and a beam splitter. The first light-guide element includes a first surface and a second surface. The optical element corresponds to the first surface. The first optical fiber is contacted with the second surface. The beam splitter is attached to the first surface, the beam splitter partially reflects and partially transmits a light beam striking thereon. A refractive index of the beam splitter is different from a refractive index of the first light-guide element.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 24, 2015
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Hsien Liao, Ming-Yi Huang, Te-Hsuan Yang
  • Publication number: 20150214394
    Abstract: An opto-electrical conversion structure includes a substrate, a first semiconductor structure, and a second semiconductor structure. The substrate has a first surface and a second surface opposite to each other. The first surface has a plurality of micro-structures and a plurality of nano-structures. The nano-structures are distributed on the surface of the micro-structures, and have heights of about 500 nm to about 900 nm. The first semiconductor structure is disposed on the first surface of the substrate. The second semiconductor structure is disposed on the second surface of the substrate.
    Type: Application
    Filed: June 6, 2014
    Publication date: July 30, 2015
    Inventors: Ming-Yi HUANG, Po-Chuan YANG, Jr-Hau HE, Hsin-Ping WANG, Tzu-Yin LIN