Patents by Inventor Ming-Yu Chang
Ming-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
-
Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
-
Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
-
Publication number: 20240161844Abstract: An antifuse-type non-volatile memory and a control method for the antifuse-type non-volatile memory are provided. During a program action of a program cycle, a timing controller generates a timing control signal. According to the timing control signal, a word line driver is controlled to provide an on voltage and an off voltage to an activated word line. In a total time period of plural on periods, the program current is sufficient to rupture a gate oxide layer of an antifuse transistor in the selected memory cell, and a heating process is completed. Consequently, the gate oxide layer of the antifuse transistor is in a solid rupture state. Consequently, the program action can be successfully performed on the selected memory cell.Type: ApplicationFiled: September 20, 2023Publication date: May 16, 2024Inventors: Chia-Fu CHANG, Jen-Yu PENG, Ming-Hsuan TAN
-
Publication number: 20240154025Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metalType: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
-
Publication number: 20240135187Abstract: Provided are computing systems, methods, and platforms that train query processing models, such as large language models, to perform query intent classification tasks by using retrieval augmentation and multi-stage distillation. Unlabeled training examples of queries may be obtained, and a set of the training examples may be augmented with additional feature annotations to generate augmented training examples. A first query processing model may annotate the retrieval augmented queries to generate inferred labels for the augmented training examples. A second query processing model may be trained on the inferred labels, distilling the query processing model that was trained with retrieval augmentation into a non-retrieval augmented query processing model. The second query processing model may annotate the entire set of unlabeled training examples. Another stage of distillation may train a third query processing model using the entire set of unlabeled training examples without retrieval augmentation.Type: ApplicationFiled: October 22, 2023Publication date: April 25, 2024Inventors: Krishna Pragash Srinivasan, Michael Bendersky, Anupam Samanta, Lingrui Liao, Luca Bertelli, Ming-Wei Chang, Iftekhar Naim, Siddhartha Brahma, Siamak Shakeri, Hongkun Yu, John Nham, Karthik Raman, Raphael Dominik Hoffmann
-
Patent number: 11953877Abstract: Manufacturing of a shoe or a portion of a shoe is enhanced by executing various shoe-manufacturing processes in an automated fashion. For example, information describing a shoe part may be determined, such as an identification, an orientation, a color, a surface topography, an alignment, a size, etc. Based on the information describing the shoe part, automated shoe-manufacturing apparatuses may be instructed to apply various shoe-manufacturing processes to the shoe part, such as a pickup and placement of the shoe part with a pickup tool.Type: GrantFiled: October 20, 2022Date of Patent: April 9, 2024Assignee: NILE, Inc.Inventors: Dragan Jurkovic, Patrick Conall Regan, Chih-Chi Chang, Chang-chu Liao, Ming-Feng Jean, Kuo-Hung Lee, Yen-Hsi Liu, Hung-Yu Wu
-
Publication number: 20240113032Abstract: Interconnect structure packages (e.g., through silicon vias (TSV) packages, through interlayer via (TIV) packages) may be pre-manufactured as opposed to forming TIVs directly on a carrier substrate during a manufacturing process for a semiconductor die package at backend packaging facility. The interconnect structure packages may be placed onto a carrier substrate during manufacturing of a semiconductor device package, and a semiconductor die package may be placed on the carrier substrate adjacent to the interconnect structure packages. A molding compound layer may be formed around and in between the interconnect structure packages and the semiconductor die package.Type: ApplicationFiled: April 25, 2023Publication date: April 4, 2024Inventors: Kai-Fung CHANG, Chin-Wei LIANG, Sheng-Feng WENG, Ming-Yu YEN, Cheyu LIU, Hung-Chih CHEN, Yi-Yang LEI, Ching-Hua HSIEH
-
Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
-
Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
-
Publication number: 20240077656Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Wen-Yu TSAI, Heng-Yi SU, Ming-Ta CHOU, Chien-Pang CHANG, Kuo-Chiang CHU
-
Publication number: 20240077657Abstract: An imaging lens assembly includes a first optical element and a low-reflection layer. The first optical element has a central opening, and includes a first surface, a second surface and a first outer diameter surface. The first outer diameter surface is connected to the first surface and the second surface. The low-reflection layer is located on at least one of the first surface and the second surface, and includes a carbon black layer, a nano-microstructure and a coating layer. The nano-microstructure is directly contacted with and connected to the carbon black layer, and the nano-microstructure is farther from the first optical element than the carbon black layer from the first optical element. The coating layer is directly contacted with and connected to the nano-microstructure, and the coating layer is farther from the first optical element than the nano-microstructure from the first optical element.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Wen-Yu TSAI, Heng-Yi SU, Ming-Ta CHOU, Chien-Pang CHANG, Kuo-Chiang CHU
-
Publication number: 20240080505Abstract: A method, comprising: detecting an outage of at least one functionality in a live streaming; performing an first operation toward a second user terminal; storing data of the first operation in a database of the first user terminal; and displaying an effect corresponding to the first operation during the outage. The present disclosure may store the data of operation performed by the user terminal during outage and process the operation after the outage is recovered. Therefore, the streamers and viewers may feel interested and satisfied, instead of feeling anxious, and the user experience may be enhanced.Type: ApplicationFiled: June 23, 2023Publication date: March 7, 2024Inventors: Yung-Chi HSU, Hsing-Yu TSAI, Chia-Han CHANG, Yi-Jou LEE, Ming-Che CHENG
-
Patent number: 11923326Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.Type: GrantFiled: July 27, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Yu Chang, Ming-Da Cheng, Ming-Hui Weng
-
Publication number: 20240071776Abstract: A chip packaging structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a dam and a metal shielding layer. The conductive substrate includes a substrate, vias and electrodes. The substrate has first and second board surfaces opposite to each other. The vias penetrate through the first board surface and the second board surface, and a part of the vias is disposed in a first die-bonding region on which a chip is to be arranged. The electrodes extend from the first board surface to the second board surface through the vias. The dam is formed on the first board surface to surround the first die-bonding region, and the dam has a height higher than that of the chip. The metal shielding layer covers the dam and a part of the first board surface that do not overlap with the electrodes.Type: ApplicationFiled: December 2, 2022Publication date: February 29, 2024Inventors: DEI-CHENG LIU, CHIA-SHUAI CHANG, MING-YEN PAN, JIAN-YU SHIH, JHIH-WEI LAI, SHIH-HAN WU
-
Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
-
Publication number: 20230266651Abstract: The disclosure provides a laser lighting system. The laser lighting system includes a microcontroller, a motor, a fluorescent color wheel and a detection circuit. The motor drives the fluorescent color wheel to rotate. The detection circuit is configured to detect a detected signal from the fluorescent color wheel. When a synchronous signal changes, the microcontroller compares the detected signal to the synchronous signal, in order to control the output current signal for driving the motor, and to decrease the phase variation between the detected signal and the synchronous signal until the phase difference between the detected signal and the synchronous signal maintain at a constant value.Type: ApplicationFiled: August 29, 2022Publication date: August 24, 2023Inventors: Chi-Yin HO, Ming-Yu CHANG, Yuan-Ming HSU
-
Patent number: 9331895Abstract: A method for controlling an electronic device and an electronic apparatus are provided. A position of the electronic apparatus in a spatial area is obtained. A scene of the spatial area where the electronic apparatus is located is displayed in a display unit. A position of a controllable target apparatus included in the scene is obtained by using the position of the electronic apparatus and searching in a target apparatus distribution database of the spatial area, and a relative position of the controllable target apparatus and the electronic apparatus is obtained. According to the obtained position of the controllable target apparatus, an apparatus image layer corresponding to the controllable target apparatus is displayed at a corresponding position of the scene. When the apparatus image layer receives an enabling signal, a controlling command is transmitted to the controllable target apparatus corresponding to the apparatus image layer.Type: GrantFiled: May 2, 2013Date of Patent: May 3, 2016Assignee: COMPAL ELECTRONICS, INC.Inventors: Cheng-Lung Lin, Hsing-Yui Yang, Ming-Yu Chang, Ching-Hsiang Chiang
-
Patent number: 9069463Abstract: An operating method for dynamically adjusting a touch apparatus is disclosed herein. The touch apparatus includes a storage component and a touch component. The storage component is configured to store at least one application, and a plurality of weights of touch motion modes and touch motion modes corresponding to the application. The operating method includes determining whether execution of the application has started. When execution of the application has started, a plurality of touch motions corresponding to the executed application are received through the touch component. At least one of the weights of touch motion modes corresponding to the executed application is adjusted according to the touch motions. At least one of touch parameters is adjusted according to the weights of touch motion modes corresponding to the executed application.Type: GrantFiled: September 18, 2013Date of Patent: June 30, 2015Assignee: COMPAL ELECTRONICS, INC.Inventors: Ming-Yu Chang, Chun-Ming Wang, Yun-Rui Chen, Chia-Hui Chen, Wen-Han Li, Fei-Zhi Guo, Ping-Hsien Niu
-
Publication number: 20140285447Abstract: An operating method for dynamically adjusting a touch apparatus is disclosed herein. The touch apparatus includes a storage component and a touch component. The storage component is configured to store at least one application, and a plurality of weights of touch motion modes and touch motion modes corresponding to the application. The operating method includes determining whether execution of the application has started. When execution of the application has started, a plurality of touch motions corresponding to the executed application are received through the touch component. At least one of the weights of touch motion modes corresponding to the executed application is adjusted according to the touch motions. At least one of touch parameters is adjusted according to the weights of touch motion modes corresponding to the executed application.Type: ApplicationFiled: September 18, 2013Publication date: September 25, 2014Applicant: COMPAL ELECTRONICS, INC.Inventors: Ming-Yu CHANG, Chun-Ming WANG, Yun-Rui CHEN, Chia-Hui Chen, Wen-Han LI, Fei-Zhi GUO, Ping-Hsien NIU