Patents by Inventor Ming-Yu Lin
Ming-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
-
Publication number: 20240170543Abstract: A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu KAO, Shih-Yao LIN, Chen-Ping CHEN, Chih-Han LIN, Ming-Ching CHANG, Chao-Cheng CHEN
-
Publication number: 20240170336Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. The semiconductor device includes a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers. The semiconductor device includes a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface. A portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chao-Cheng Chen, Chih-Han Lin, Chen-Ping Chen, Ming-Ching Chang, Shih-Yao Lin, Chih-Chung Chiu
-
Publication number: 20240161403Abstract: Text-to-image generation generally refers to the process of generating an image from one or more text prompts input by a user. While artificial intelligence has been a valuable tool for text-to-image generation, current artificial intelligence-based solutions are more limited as it relates to text-to-3D content creation. For example, these solutions are oftentimes category-dependent, or synthesize 3D content at a low resolution. The present disclosure provides a process and architecture for high-resolution text-to-3D content creation.Type: ApplicationFiled: August 9, 2023Publication date: May 16, 2024Inventors: Chen-Hsuan Lin, Tsung-Yi Lin, Ming-Yu Liu, Sanja Fidler, Karsten Kreis, Luming Tang, Xiaohui Zeng, Jun Gao, Xun Huang, Towaki Takikawa
-
Publication number: 20240157469Abstract: The present application provides a method for determining a stability of a welding equipment. The method includes acquiring initial welding images of the welding equipment; obtaining at least one welding spot position of each of at least one welded workpiece in each initial welding image by processing the initial welding images; determining a welding center position of each welded workpiece based on the at least one welding spot position of each welded workpiece, and obtaining welding center positions of all welded workpieces comprised in the initial welding images; and determining a stability of welding equipment based on the welding center positions of all welded workpieces. The method determines whether the welding equipment is stable by analyzing the welding images, thereby improving an accuracy of a detection of a stability of the welding equipment.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: YEN TSAN, TSUNG-JU LIN, CHEN-TING WU, MING-TAO LUO, JUN-MING HUANG, TAI-YU CHOU, QUAN-XI CHEN
-
Publication number: 20240154025Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metalType: ApplicationFiled: January 10, 2024Publication date: May 9, 2024Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chih-Han Lin, Ming-Ching Chang, Chao-Cheng Chen
-
Publication number: 20240145327Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.Type: ApplicationFiled: December 27, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chang-Jung Hsueh, Cheng-Nan Lin, Wan-Yu Chiang, Wei-Hung Lin, Ching-Wen Hsiao, Ming-Da Cheng
-
Publication number: 20240145460Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.Type: ApplicationFiled: January 3, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Min WU, Ming-Dou KER, Chun-Yu LIN, Li-Wei CHU
-
Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
-
Patent number: 11961770Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.Type: GrantFiled: November 4, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Han Lin, Chien-Fa Lee, Hsu-Shui Liu, Jiun-Rong Pai, Sheng-Hsiang Chuang, Surendra Kumar Soni, Shou-Wen Kuo, Wu-An Weng, Gary Tsai, Chien-Ko Liao, Ya Hsun Hsueh, Becky Liao, Ethan Yu, Ming-Chi Tsai, Kuo-Yi Liu
-
Publication number: 20240120854Abstract: A triboelectric nanogenerating device is configured for providing an electric power to an electronic device and the triboelectric nanogenerating device includes at least one scaly triboelectric membrane configured for providing the electric power to the electronic device by frictional electrification. The at least one scaly triboelectric membrane includes a keratin and a polyvinyl alcohol, the at least one scaly triboelectric membrane has a first triboelectric surface, and the first triboelectric surface of the at least one scaly triboelectric membrane includes a plurality of scaly layers. Each of the scaly layers is arranged in order and extends along an orienting direction. A distal end of each of the scaly layers has a plurality of saw-tooth structures.Type: ApplicationFiled: February 6, 2023Publication date: April 11, 2024Inventors: Zong-Hong Lin, Ming-Zheng Huang, Hsuan-Yu Yeh, An-Rong Chen, Yao-Hsuan Tseng
-
Publication number: 20240107454Abstract: A User Equipment (UE) including a wireless transceiver and a controller is provided. The wireless transceiver performs wireless transmission and reception to and from one or more peer UEs. The controller determines a Sidelink (SL) Discontinuous Reception (DRX) configuration set, and applies the SL DRX configuration set to enable a DRX operation for SL communications with the peer UEs via the wireless transceiver; wherein the SL DRX configuration set is determined based on one of the following: one or more types of one or more SL services which the UE is participating with the peer UEs; one or more SL DRX configurations received from the peer UEs; and control information received from a Base Station (BS).Type: ApplicationFiled: December 8, 2023Publication date: March 28, 2024Applicant: MEDIATEK INC.Inventors: Guan-Yu LIN, Ming-Yuan CHENG, Nathan Edward TENNY, Xuelong WANG
-
Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
-
Publication number: 20240096893Abstract: A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.Type: ApplicationFiled: November 24, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chao-Cheng Chen, Chih-Han Lin, Ming-Ching Chang, Wei-Liang Lu, Kuei-Yu Kao
-
Publication number: 20240088119Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
-
Patent number: 11916084Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.Type: GrantFiled: August 24, 2022Date of Patent: February 27, 2024Assignee: AUO CorporationInventors: Chun-Yu Lin, Kun-Cheng Tien, Jia-Long Wu, Ming-Lung Chen, Shu-Hao Huang
-
Publication number: 20210302366Abstract: Present disclosure provides a method for pathogen detection, including operations that applying a biological sample to a culturing chamber comprising an interacting agent; driving a sensor electrically coupled to the biological sample in the culturing chamber; measuring an electrical signal from the sensor; and obtaining pathogen-related information of the biological sample based on the electrical signal.Type: ApplicationFiled: March 29, 2021Publication date: September 30, 2021Inventors: Hardy Wai Hong CHAN, Yi-Shao LIU, Chihchung CHEN, Ming-Yu LIN, Hao LEE
-
Patent number: 10787657Abstract: In various embodiments methods are provided for delivering an agent of interest (e.g., protein, antibody, nucleic acid) into cells. In certain embodiments the method comprises contacting the cells with anisotropic magnetic particles in the presence of the agent; and applying a substantially uniform magnetic field to said magnetic particles where movement of said particles induced by said magnetic field introduces transient openings into said cell facilitating entry of said agent of interest into said cells.Type: GrantFiled: December 21, 2016Date of Patent: September 29, 2020Assignee: The Regents of the University of CaliforniaInventors: Pei-Yu E. Chiou, Michael A. Teitell, Ming-Yu Lin, Yi-Chien Wu, Jessica Zhou
-
Patent number: 10500749Abstract: A cutting machine includes a platform, two supporting elements, a guiding plate, a handle and a blade assembly. The supporting elements are supported on the platform. Each of the supporting elements includes a space. The guiding plate is inserted in the space of the first supporting element and includes a slot. The handle includes a pivoting plate and an axle. The pivoting plate is inserted in the space of the second supporting element, and includes a primary aperture and a secondary aperture. The axle is inserted in the primary aperture of the pivoting plate and an aperture of the second supporting element. The blade assembly includes a blade and two pins. The first pin is inserted in an aperture of the blade and movably inserted in the slot. The second pin is inserted in another aperture of the blade and the secondary aperture of the pivoting plate.Type: GrantFiled: May 22, 2017Date of Patent: December 10, 2019Inventor: Ming-Yu Lin
-
Patent number: 10299678Abstract: An apparatus for detecting conductance parameter of high protein body fluid sample is provided. The apparatus includes at least one liquid collection element, and at least two electrodes horizontally aligned in the liquid collection element. Also provided are methods for detecting dehydration in a subject, comprising the steps of measuring the conductance parameter of the saliva of the subject.Type: GrantFiled: April 3, 2017Date of Patent: May 28, 2019Assignees: CHANG GUNG MEMORIAL HOSPITAL, CHIAYI, NATIONAL APPLIED RESEARCH LABORATORIES, NATIONAL TAIWAN UNIVERSITYInventors: Jen-Tsung Yang, Leng-Chieh Lin, I-Neng Lee, Jo-Wen Huang, Jer-Liang Andrew Yeh, Ming-Yu Lin, Yen-Pei Lu, Chih-Ting Lin, Chia-Hong Gao