Abstract: The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

Abstract: The present disclosure provides multi-channel receiver and multi-channel reception method.

Abstract: The present disclosure provides multi-channel receiver and multi-channel reception method.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: The present disclosure provides a multi-phase clock signal phase difference detection and calculation circuit and method, and a digital phase modulation system. The detection and calculation circuit includes an auxiliary digital-to-time conversion circuit, a main digital-to-time conversion circuit, a phase detector, and a state machine. The auxiliary digital-to-time conversion circuit selects a first phase clock signal and outputs an auxiliary clock signal, adjusts the phase of the auxiliary clock signal; the phase detector detects the phases of the auxiliary clock signal and a target clock signal output by the main digital-to-time conversion circuit; the state machine adjusts the phase of the auxiliary clock signal, and adjusts the phase of the target clock signal. When the phase difference between the two signals is zero, the amount of phase adjustment by the main digital-to-time conversion circuit is the phase difference between the first phase clock signal and the second phase clock signal.

Abstract: The present disclosure provides a linear calibration system for a time-to-digital converter and a method thereof, and a digital phase-locked loop. The linear calibration system includes a digitally controlled reference delay circuit for receiving a first clock signal and delaying the first clock signal to generate a reference clock signal, a time-to-digital conversion circuit including at least two time-to-digital converters, and a state machine. The time-to-digital conversion circuit receives the first clock signal and the reference clock signal, delays the first clock signal to generate a first delay signal, compares a phase of the first delay signal with a phase of the reference clock signal, and outputs a phase detection result signal. The state machine generates a delay control signal for controlling the digitally controlled reference delay circuit, adjusts a calibration control signal to align the phases of the first delay signal and the reference clock signal.

Abstract: A low noise amplifier includes a preamplifier, first differential amplifiers, second differential amplifiers, a signal adder, and a load circuit. The preamplifier receives an input signal, and amplifies the input signal to generate a first signal. The input signal and the first signal have the same phase. The first differential amplifiers receive the first signal and a first reference signal and generate a first output differential signal pair. The second differential amplifiers receive the input signal and a second reference signal and generate a second output differential signal pair. The signal adder adds up the first output differential signal pair and the second output differential signal pair. The load circuit is coupled to the signal adder, and generates a third output differential signal pair according to the addition result.

Abstract: The present disclosure provides a reference clock signal injected phase locked loop circuit and an offset calibration method. The reference clock signal injected phase locked loop circuit includes a first pulse generator, a second pulse generator, a state machine, a pulse selection and amplification circuit, a voltage controlled delay line, a phase detector, and a filter, and forms an offset calibration loop, a phase locked loop, a voltage controlled oscillator loop, and an injection locked loop. The state machine disconnects the phase locked loop and the voltage controlled oscillator loop and enables the offset calibration loop to calibrate the phase detector; the state machine enables the phase locked loop and the voltage controlled oscillator loop and locks a signal of the second pulse generator; and the state machine enables the injection locked loop for injecting a first pulse signal of the first pulse generator.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Abstract: A radio frequency (RF) signal transceiver is provided. The RF signal transceiver includes a first transformer, a signal transceiving processor, a signal receiving amplifier, and a signal transmitting amplifier. The first transformer is coupled to an antenna through a first end of a primary side, and two endpoints of a secondary side of the first transformer receive and transmit a pair of differential signals. The signal transceiving processor receives a pair of input differential signals from the secondary side of the first transformer and generates a pair of processed differential signals. The signal receiving amplifier is coupled to the signal transceiving processor and is configured to receive and amplify the pair of processed differential signals. The signal transmitting amplifier is coupled to the secondary side of the first transformer and provides a pair of transmission differential signals to the secondary side.

Abstract: A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.

Abstract: A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal.

Abstract: The digital delay-locked loop includes: a frequency divider, used to perform frequency division processing on a first clock-signal according to frequency division information, and output a second clock-signal; a signal-selector, used to select the first or second clock-signal as a third clock-signal according to the selection signal output; a delay line, used to delay the third clock-signal according to the delay control signal, and output a fourth clock-signal; a phase detector, used to receive the third and fourth clock-signals, perform phase detection processing, and output a phase detection judgment signal; and a state machine connected with the frequency divider, signal-selector, delay line and phase detector, used to adjust and control the frequency division information, the selection signal and the delay control signal output according to the phase detection judgment signal and a set state logic, to achieve that delay time of the fourth clock-signal relative to the first clock-signal.

Abstract: The digital delay-locked loop includes: a frequency divider, used to perform frequency division processing on a first clock-signal according to frequency division information, and output a second clock-signal; a signal-selector, used to select the first or second clock-signal as a third clock-signal according to the selection signal output; a delay line, used to delay the third clock-signal according to the delay control signal, and output a fourth clock-signal; a phase detector, used to receive the third and fourth clock-signals, perform phase detection processing, and output a phase detection judgment signal; and a state machine connected with the frequency divider, signal-selector, delay line and phase detector, used to adjust and control the frequency division information, the selection signal and the delay control signal output according to the phase detection judgment signal and a set state logic, to achieve that delay time of the fourth clock-signal relative to the first clock-signal.

Abstract: A quadrature phase signal generator comprises a relative delay unit, a phase detector, a first amplifier and a loop filter. The relative delay unit delays differential input signals and generates four delayed signals. The phase detector generates quadrature four phase output signals, a first voltage signal and a second voltage signal according to the four delayed signals. A difference of the first and the second voltage signals indicates a phase error of the quadrature four phase output signals. The first amplifier amplifies the voltage difference of the first and the second voltage signals. The loop filter filters the amplified voltage difference and generates a tuning voltage signal. The loop filter is further communicatively coupled to the relative delay unit. The relative delay unit adjusts a delay of the quadrature four phase delayed signals according to the tuning voltage signal.

Abstract: A quadrature phase signal generator comprises a relative delay unit, a phase detector, a first amplifier and a loop filter. The relative delay unit delays differential input signals and generates four delayed signals. The phase detector generates quadrature four phase output signals, a first voltage signal and a second voltage signal according to the four delayed signals. A difference of the first and the second voltage signals indicates a phase error of the quadrature four phase output signals. The first amplifier amplifies the voltage difference of the first and the second voltage signals. The loop filter filters the amplified voltage difference and generates a tuning voltage signal. The loop filter is further communicatively coupled to the relative delay unit. The relative delay unit adjusts a delay of the quadrature four phase delayed signals according to the tuning voltage signal.