Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A subpixel structure includes a substrate and a light emitting diode chip. The light emitting diode chip is disposed on the substrate. The light emitting diode chip has a chip area and a light emitting area, and the light emitting area is less than or equal to one tenth of the chip area.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

Abstract: A gear module includes a rotating cylinder, a first planetary gear set, a second planetary gear set, a concave-convex structure, and a limit bearing set. The first planetary gear set is accommodated in the rotating cylinder and includes a driven gear; the second planetary gear set includes a positioning frame, second planetary gears pivoted to a positioning frame, a driven gear engaged with the second planetary gears, and the positioning frame has a through hole; the concave-convex structure includes a convex column extended from the rotating cylinder and a concave hole formed on the positioning frame, the convex column is plugged into the concave hole; the limit bearing set includes a first ball bearing sheathing the driven gear and mounted between the driven gear and the through hole, and a second ball bearing sheathing the convex column and mounted between the convex column and the concave hole.

Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.

Abstract: A semiconductor device includes a substrate, a dielectric layer disposed over the substrate, and an interconnect structure extending through the dielectric layer. The dielectric layer includes a low-k dielectric material which includes silicon carbonitride having a carbon content ranging from about 30 atomic % to about 45 atomic %. The semiconductor device further includes a thermal dissipation feature extending through the dielectric layer and disposed to be spaced apart from the interconnect structure.

Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.

Abstract: A circuit includes power supply and reference nodes, a protection circuit including a first output terminal and first and second series of n-type HEMTs coupled between the power supply and reference nodes, and a gate driver including a second output terminal and third through fifth series of n-type HEMTs coupled between the power supply and reference nodes. The first HEMT series controls a first node voltage responsive to a power supply node voltage, the second HEMT series controls a first output terminal voltage responsive to the first node voltage, the third HEMT series controls an internal signal on a second node responsive to the first output terminal voltage and to an input signal, the fourth HEMT series controls a third node voltage responsive to the internal signal, and the fifth HEMT series controls a signal at the second output terminal responsive to the internal signal and the third node voltage.

Abstract: A circuit includes a power supply voltage node having a power supply voltage level, a protection circuit that generates a first signal having first and second logical voltage levels based on the power supply voltage level, and a gate driver. The gate driver includes a first n-type HEMT between the power supply voltage node and a first node, a second n-type HEMT between the first node and a power supply reference node, and a DCFL circuit between the first node and an output terminal. A gate of the first n-type HEMT receives the first signal, a gate of the second n-type HEMT receives a second signal, and the DCFL circuit generates a third signal at the output terminal based on the second signal when the first signal has the first logical voltage level, and as a DC voltage level when the first signal has the second logical voltage level.

Abstract: A filter structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, a dielectric layer between the ground plane and the plate, the ground plane, the dielectric layer, and the plate thereby being configured as a capacitive device, and an inductive device in a third metal layer of the IC package. The inductive device is electrically connected to the plate, and the plate and the inductive device are configured to have a resonance frequency greater than 1 GHz.

Abstract: Systems, methods, and devices are provided for a circuit for generating a pulse output having a controllable pulse width. Systems and methods may include a delay line having a plurality of stages. A delay per stage calculation circuit is configured to determine a per-stage delay of the delay line using a first clock input. A pulse generation circuit is configured to generate the pulse output using the delay line based on the per-stage delay using a second clock input, the second clock input having a lower frequency than the first clock input.