Abstract: The present invention relates to a voltage-to-current transconductance stage arrangement comprising a single-ended input, an emitter-coupled pair of transistors, comprising a first transistor and a second transistor, the emitter of a third transistor, being connected to the collector of said first transistor, and differential output. It further comprises at least one common-collector transistor comprising a fourth transistor connected to the base of said second transistor preferably or optionally also and a fifth transistor connected to the base of said third transistor. The size of said fourth, or fourth and fifth transistors considerably exceed the sizes of said second and third transistors. They are biased at ‘off-state’. An extra inductor at the collector of the transistor may be applied to further increase linearity.

Abstract: The present invention relates to a sub-harmonically pumped conversion mixer arrangement comprising a transistor arrangement and transistor terminals for application of a local oscillator, LO-, signal and application of a radio frequency, RF-, signal and for extraction of a mixed intermediate frequency, IF-, signal. The transistor arrangement comprises at least one NMOS transistor and at least one PMOS transistor. The drain of said at least one NMOS transistor is interconnected with the drain of said at least one PMOS transistor, and in that the gate of said at least one PMOS transistor is interconnected with the gate of said at least one NMOS transistor.

Abstract: The present invention relates to a voltage-to-current transconductance stage arrangement comprising a single-ended input, an emitter-coupled pair of transistors, comprising a first transistor and a second transistor, the emitter of a third transistor, being connected to the collector of said first transistor, and differential output. It further comprises at least one common-collector transistor comprising a fourth transistor connected to the base of said second transistor preferably or optionally also and a fifth transistor connected to the base of said third transistor. The size of said fourth, or fourth and fifth transistors considerably exceed the sizes of said second and third transistors. They are biased at ‘off-state’. An extra inductor at the collector of the transistor may be applied to further increase linearity.