Patents by Inventor Mingsheng Han

Mingsheng Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • VIAS WITH MULTICONNECTION VIA STRUCTURES
    Publication number: 20200387581
    Abstract: Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 10, 2020
    Inventors: Ping-San Tzeng, Mingsheng Han, Yucheng Wang
  • Vias with multiconnection via structures
    Patent number: 10853553
    Abstract: Improving an initial via in a circuit comprises: obtaining layout information associated with an initial via structure in a circuit, the initial via comprising an initial lower metal enclosure and an initial upper metal enclosure connected by an initial cut; determining layout information associated with a multiconnection via structure comprising a plurality of sibling vias having at least one additional upper metal enclosure and at least one additional lower metal enclosure; updating the layout information associated with the initial via with the layout information associated with the multiconnection via structure; and outputting the updated layout information. The plurality of sibling vias are connected by a plurality of corresponding sibling cuts, and the multiconnection via structure has lower resistance than the initial via structure. In some embodiments, the multiconnection via is efficiently represented in using a master template.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 1, 2020
    Assignee: Avatar Integrated Systems, Inc.
    Inventors: Ping-San Tzeng, Mingsheng Han, Yucheng Wang
  • Sibling wire routing
    Patent number: 10776554
    Abstract: A placed netlist is routed. A circuit is obtained that implements the placed netlist. A net in the circuit is identified to be enhanced. Space adjacent to a wire associated with the net that would accommodate a parallel wire is reserved.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 15, 2020
    Assignee: Avatar Integrated Systems, Inc.
    Inventors: Ping-San Tzeng, Mingsheng Han